SDCFAA-004G SanDisk, SDCFAA-004G Datasheet - Page 19

• Manufacturer Part Number: SDCFAA-004G
• Manufacturer: SanDisk
• Type: CompactFlashr

Specifications of SDCFAA-004G

• Density: 4GByte
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Package Type: Not Required
• Mounting: Socket
• Pin Count: 50
• Operating Temperature Classification: Commercial
• Programmable: Yes
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SanDisk CompactFlash Card OEM Product Manual
02/09, Rev. 1.0 ii © 2007 - 2009 SanDisk Corporation. SanDisk Confidential, subject to all applicable non-disclosure agreements.
READY
(PC Card Memory Mode)
-IREQ
(PC Card I/O Mode)
INTRQ
(True IDE Mode)
-REG
(PC Card Memory Mode –
Except Ultra DMA
Protocol Active)
Attribute Memory Select
-REG
(PC Card I/O Mode –
Except Ultra DMA
Protocol Active)
-DMACK
(PC Card Memory Mode
when Ultra DMA Protocol
Active)
DMACK
(PC Card I/O Mode when
Ultra DMA Protocol
Active)
-DMACK
(True IDE Mode)
Signal Name
O
I
Dir.
37
44
Pin
19
In Memory Mode, this signal is set high
when the CompactFlash Storage Card or
CF+ Card is ready to accept a new data
transfer operation and is held low when
the card is busy.
At power up and at Reset, the READY
signal is held low (busy) until the
CompactFlash Storage Card or CF+ Card
has completed its power up or reset
function. No access of any type should be
made to the CompactFlash Storage Card
or CF+ Card during this time.
Note, however, that when a card is
powered up and used with RESET
continuously disconnected or asserted,
the Reset function of the RESET pin is
disabled. Consequently, the continuous
assertion of RESET from the application
of power shall not cause the READY
signal to remain continuously in the busy
state.
I/O Operation – After the CompactFlash
Storage Card or CF+ Card has been
configured for I/O operation, this signal is
used as -Interrupt Request. This line is
strobed low to generate a pulse mode
interrupt or held low for a level mode
interrupt.
In True IDE Mode signal is the active high
Interrupt Request to the host.
This signal is used during Memory Cycles
to distinguish between Common Memory
and Register (Attribute) Memory
accesses. High for Common Memory, Low
for Attribute Memory.
In PC Card Memory Mode, when Ultra
DMA Protocol is supported by the host
and the host has enabled Ultra DMA
protocol on the card the, host shall keep
the -REG signal
negated during the execution of any DMA
Command by the device.
The signal shall also be active (low) during
I/O Cycles when the I/O address is on the
Bus.
In PC Card I/O Mode, when Ultra DMA
Protocol is supported by the host and the
host has enabled Ultra DMA protocol on
the card the, host shall keep the -REG
signal asserted during the execution of
any DMA Command by the device.
This is a DMA Acknowledge signal that is
asserted by the host in response to (-)
DMARQ to initiate DMA transfers.
In True IDE Mode, while DMA operations
are not active, the card shall ignore the (-)
DMACK signal, including a floating
condition.
If DMA operation is not supported by a
True IDE Mode only host, this signal
should be driven high or connected to
VCC by the host.
A host that does not support DMA mode
and implements both PC Card and True-
IDE modes of operation need not alter the
PC Card mode connections while in True-
IDE mode as long as this does not prevent
proper operation all modes.
Description
Interface Description