SLFDM44H-512MM1UI STEC, SLFDM44H-512MM1UI Datasheet - Page 10

• Manufacturer Part Number: SLFDM44H-512MM1UI
• Manufacturer: STEC
• Type: Flash Diskr

Specifications of SLFDM44H-512MM1UI

• Density: 512MByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: Not Required
• Mounting: Plug in
• Pin Count: 44
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3.18/4.75V
• Operating Supply Voltage (max): 3.465/5.25V
• Programmable: Yes
• Lead Free Status / RoHS Status: Compliant

SLFDM(40/44)(V/H)-xxx(M/G)M1U(I)
Datasheet
1.3
-DASP
D15-D00
-IOWR
-IORD
INTRQ
A2-A0
-CS0, -CS1
-CSEL
(not used on housed
modules)
-IOCS16
-PDIAG
DMARQ
-DMACK
-IORDY
-RESET
VCC
(44-pin version only)
GND
(Pin 43 present on
44-pin version only)
Key
NC
(44-pin version only)
Signal Name
Signal Descriptions
Dir
I/O
I/O
I/O
—
—
—
—
O
O
O
O
I
I
I
I
I
I
I
18, 16, 14,
24, 26, 30,
13, 15, 17
35, 33, 36
12, 10, 8,
6, 4, 3, 5,
2, 19, 22,
7, 9, 11,
37, 38
41, 42
40, 43
Pin
39
23
25
31
28
32
34
21
29
27
20
44
61000-04498-112, April 2008
1
This input/output is the Disk Active/Slave Present signal in the
Master/ Slave handshake protocol.
All Task File operations occur in byte mode on the low order
bus D00-D07 while all data transfers are 16 bit using D00-D15.
The I/O Write strobe pulse is used to clock I/O data on the
module Data bus into the Module controller registers when the
Module is configured to use the I/O interface. The clocking will
occur on the negative to positive edge of the signal (trailing
edge).
This is an I/O Read strobe generated by the host. This signal
gates I/O data onto the bus from the Module.
Signal is the active high Interrupt Request to the host.
A[2:0] are used to select the one of eight registers in the Task
File.
-CS0 is the chip select for the task file registers while –CS1 is
used to select the Alternate Status Register and the Device
Control Register.
This internally pulled up signal is used to configure the card as
a Master or Slave. When the pin is grounded, the card is
configured as a Master. When the pin is open, the card is
configured as a Slave.
Not used.
This input/output is the Pass Diagnostic signal in the
Master/Slave handshake protocol.
This signal is asserted by the device when it is ready to transfer
data to/ from the host. Data direction is controlled by -IORD and
-IOWR. This signal is used in a handshake manner with –
DMACK.
This input signal is used by host in response to DMARQ to
initiate DMA transfers.
Not used, and pulled up to VCC through a 4.7K ohm resistor.
This input pin is the active low hardware reset from the host.
Power.
Ground.
This pin is keyed to ensure cable is connected with the proper
orientation.
No connect.
Description
IDE Flash Disk Module
10