STK11C68P45I Cypress Semiconductor Corp, STK11C68P45I Datasheet - Page 3

STK11C68P45I

Manufacturer Part Number
STK11C68P45I
Description
Manufacturer
Cypress Semiconductor Corp
Type
NVSRAMr
Datasheet

Specifications of STK11C68P45I

Word Size
8b
Organization
8Kx8
Density
64Kb
Interface Type
Parallel
Access Time (max)
45ns
Operating Supply Voltage (typ)
5V
Package Type
PDIP
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temp Range
-40C to 85C
Pin Count
28
Mounting
Through Hole
Supply Current
65mA
Lead Free Status / RoHS Status
Not Compliant
SRAM READ CYCLES #1 & #2
Note g: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note h: I/O state assumes E, G < V
Note i:
SRAM READ CYCLE #1: Address Controlled
SRAM READ CYCLE #2: E Controlled
June 1999
DQ (DATA OUT)
DQ (DATA OUT)
NO.
10
11
1
2
3
4
5
6
7
8
9
ADDRESS
ADDRESS
Measured
t
t
t
t
t
t
t
t
t
t
t
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
#1, #2
I
CC
G
E
g
h
h
i
i
SYMBOLS
f
e, f
200mV from steady state output voltage.
t
t
t
t
t
t
t
t
t
t
t
ACS
RC
AA
OE
OH
LZ
HZ
OLZ
OHZ
PA
PS
Alt.
IL
and W > V
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
STANDBY
t
ELICCH
t
t
10
IH
AXQX
ELQX
t
6
PARAMETER
5
; device is continuously selected.
GLQX
8
t
GLQV
4
g
t
AVAV
2
t
ACTIVE
t
ELQV
AVQV
1
3
t
4-23
AVAV
2
g, h
STK11C68-20
MIN
20
5
5
0
0
MAX
20
22
25
8
7
7
DATA VALID
STK11C68-25
MIN
25
5
5
0
0
MAX
25
25
10
10
10
25
DATA VALID
STK11C68-35
MIN
35
5
5
0
0
(V
t
GHQZ
CC
9
MAX
t
EHQZ
35
35
15
13
13
35
7
= 5.0V + 10%)
t
EHICCL
1 1
STK11C68-45
MIN
45
5
5
0
0
STK11C68
MAX
45
45
20
15
15
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
b

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