HSP43216VC-52 Intersil, HSP43216VC-52 Datasheet - Page 10

• Manufacturer Part Number: HSP43216VC-52
• Manufacturer: Intersil

Specifications of HSP43216VC-52

• Lead Free Status / RoHS Status: Not Compliant

FIGURE 10. POLYPHASE IMPLEMENTATION OF
FIGURE 9. TRANSVERSAL IMPLEMENTATION OF
..,X2,X1,X0
†
Y(0) = 0(C0)+X0(C1)+0(C2)+X1(C3)+0(C4)+X2(C5)+0(C6)
Y(1) = X0(C0)+0(C1)+X1(C2)+0(C3)+X2(C4)+0(C5)+X3(C6)
Y(2) = 0(C0)+X1(C1)+0(C2)+X2(C3)+0(C4)+X3(C5)+0(C6)
Y(3) = X1(C0)+0(C1)+X2(C2)+0(C3)+X3(C4)+0(C5)+X4(C6)
AIN0-15
AIN0-15
...,X2,X1,X0
Clocked at CLK/2
Y0 = X0(C1)+X1(C3)+X2(C5)
Y1 = X0(C0)+X1(C2)+X2(C4)+X3(C6)
Y2 = X1(C1)+X2(C3)+X3(C5)
INTERPOLATE BY TWO HALFBAND FILTER
INTERPOLATE BY TWO HALFBAND FILTER
R
E
G
R
E
G
2
EVEN TAP FILTER
..X1,0,X0,0
ODD TAP FILTER
C0 C2 C4 C6
R
E
G
R
E
G
G
R
E
FIGURE 11B. DATA FLOW DIAGRAM FOR INTERPOLATE BY 2 FILTER MODE (INT/EXT = 0)
FIGURE 11A. DATA FLOW DIAGRAM FOR INTERPOLATE BY 2 FILTER MODE (INT/EXT = 1)
C1 C3 C5
10
7 TAP HALFBAND FILTER
G
R
E
R
E
G
C0 C1 C2 C3 C4 C5 C6
†
†
R
E
G
R
E
G
1
..,Y5,Y3,Y1
..,Y4,Y2,Y0
1
1
1
M
U
X
R
E
G
R
E
G
..,Y2,Y1,Y0
†
R
E
G
†
R
E
G
...,Y1,Y0
PIPELINE DELAY 2-35
†
PIPELINE DELAY 19
†
GROUP DELAY 19
GROUP DELAY 19
†
†
PIPELINE DELAY 2-35
PIPELINE DELAY 19
GROUP DELAY 19
GROUP DELAY 19
EVEN TAP
HSP43216
ODD TAP
FILTER
EVEN TAP
FILTER
ODD TAP
FILTER
FILTER
In the polyphase implementation, the input data stream
feeds even and odd tap filters running at the input sample
rate. The interpolated sample stream is derived by
multiplexing the output of each polyphase branch into a
single data stream at twice the input sample rate. As in the
Decimate by Two example, the even or odd tap filters are
comprised of the even or odd indexed coefficients from the
original transversal filter.
The operation of the HSP43216 in Interpolate by Two mode
is analogous to the polyphase example above. In this mode
the internal data flow is routed as shown in Figure 11A and
Figure 11B. The different data flows depend on the selection
of internal or external multiplexing via INT/EXT. In this mode,
data input through AIN0-15 is fed to the even and odd
polyphase branches of the filter processor. The output of
each branch is multiplexed together to generate the output
data stream at the interpolated rate. NOTE: The output of
each polyphase branch is scaled by two to compensate
for the attenuation of one half caused by interpolation.
1
2
2
1
†
†
R
E
G
R
E
G
R
E
G
R
E
G
R
E
G
R
N
D
R
N
D
M
M
F
T
F
T
M
U
X
R
G
R
G
E
E
R
N
D
R
E
G
R
E
G
F
M
T
R
E
G
OEA
OEB
R
E
G
AOUT0-15
BOUT0-15
OEA
AOUT0-15
October 6, 2008
FN3365.10