HSP43216VC-52 Intersil, HSP43216VC-52 Datasheet - Page 15

• Manufacturer Part Number: HSP43216VC-52
• Manufacturer: Intersil

Specifications of HSP43216VC-52

• Lead Free Status / RoHS Status: Not Compliant

†
As in the other modes, the operation of the HSP43216 in
Quadrature to real Conversion mode is analogous to that of
the polyphase solution described above. The data flow
diagrams for this particular mode are shown in Figures 21A
and 21B.
If Internal Multiplexing is specified (INT/EXT = 1), the real
and imaginary components of the quadrature input are fed
through AIN0-15 and BIN0-15 and processed on the upper
and lower legs respectively (see Figure 21A). Each
component of the complex input is interpolated, mixed with
the non-zero sine and cosine terms of the quadrature LO,
and multiplexed together into a real output sample stream
through AOUT0-15. Prior to the output multiplexer, the upper
and lower processing legs each run at the input data rate of
CLK/2 as indicated by the “†” marking the various registers
and processing elements in Figure 21A. The complex input
sample stream may be synchronized with the zero degree
phase of the up converters quadrature LO by asserting the
SYNC control input one cycle prior to the targeted data
sample as shown in Figure 22. This ensures that the real
sample input on the upper processing leg will be mixed with
the zero degree cosine term. The minimum pipeline delay
through the real processing leg (upper leg) is 15 CLK’s and
the delay through the imaginary processing leg (lower leg) is
48 CLK’s.
Clock at Input data rate, CLK/2
BIN0-15
AIN0-15
BIN0-15
AIN0-15
R
E
G
R
E
G
FIGURE 21A. DATA FLOW DIAGRAM FOR QUADRATURE TO REAL CONVERSION MODE (INT/EXT = 1)
FIGURE 21B. DATA FLOW DIAGRAM FOR QUADRATURE TO REAL CONVERSION MODE (INT/EXT = 0)
R
G
R
G
E
E
R
E
G
R
E
G
R
E
G
R
E
G
†
†
R
E
G
R
E
G
15
G
R
E
G
R
E
1
1
1
1
†
R
E
G
†
R
E
G
†
†
G
R
E
PIPELINE DELAY 2-35
†
†
G
R
E
PIPELINE DELAY 19
GROUP DELAY 19
GROUP DELAY 19
PIPELINE DELAY 2-32
EVEN TAP
PIPELINE DELAY 19
ODD TAP
GROUP DELAY 19
GROUP DELAY 19
FILTER
FILTER
EVEN TAP
ODD TAP
FILTER
FILTER
HSP43216
If external multiplexing is selected (INT/EXT = 0), output
from the upper and lower processing legs exit through
AOUT0-15 and BOUT0-15 for multiplexing into a single data
stream off chip (see Figure 21B).This allows the processing
legs to run at the maximum CLK rate which coincides with
an interpolated output data rate of up to 104 MSPS.
NOTE: The output on BOUT0-15 precedes that on
AOUT0-15 in sample order. This requires a multiplexing
scenario which selects BOUT0-15 then AOUT0-15 on each
CLK of the HSP43216. With external multiplexing, the
minimum pipeline delay through the upper processing leg is
9 CLK’s and the pipeline delay through the lower processing
leg is 26 CLK’s as shown in Figure 21B. The SYNC control
input is used as described in the preceding paragraph.
FIGURE 22. DATA SYNCHRONIZATION WITH PROCESSING
AIN0-15
BIN0-15
2,-2,2,-2,...
-2,2,-2,2,...
CLK/2
SYNC
†
G
R
E
G
R
E
2,-2,2,-2,...
-2,2,-2,2,...
†
G
R
G
R
E
E
LEGS (INT/EXT = 1)
G
R
E
0
M
U
X
R
N
D
R
N
D
M
F
T
M
R
N
D
F
T
R
G
E
M
R
E
G
F
T
R
G
E
G
G
R
E
R
E
G
R
E
OEA
OEB
AOUT0-15
AOUT0-15
BOUT0-15
OEA
October 6, 2008
FN3365.10