MC44BS374T1AEF Freescale, MC44BS374T1AEF Datasheet - Page 26

• Manufacturer Part Number: MC44BS374T1AEF
• Manufacturer: Freescale

Specifications of MC44BS374T1AEF

• Lead Free Status / RoHS Status: Compliant

High Speed I2C Compatible Bus
17.3 Level Definitions
SDA/SCL high and low levels are designed to be compatible with 0-5V and 0-3.3V SDA / SCL signals.
17.4 High Speed I
17.5 I
It The bus receiver operates the I
In write mode, each ninth data bit ( bits 9, 18, 27, 36, and 45 ) is an acknowledge bit (ACK) during which
the MCU sends a logic 1 and the Modulator circuit answers on the data line by pulling it low. Besides the
chip address, the circuit needs two or four data bytes for operation. The following sequences of data bytes
are the permitted incoming information:
SDA
SCL
STA
Example 1
Example 2
Example 3
Example 4
Note:
STA = Start condition
2
C Write Mode Format and Bus Receiver
1
Chip Address ($CA)
2
3
Table 10. Permitted Data Bytes (Incoming Information)
4
1 1 0 0 1 0 1 0 (ACK) = $CA ( hex ) in write mode
Freescale Semiconductor, Inc.
SDA
5
STA
STA
STA
STA
2
MC44BS374T1/374T1A Advance Information
For More Information On This Product,
C Compatible Bus Format
6
2
C compatible data format. The chip address ( I
...
Table 9. Chip Address (I
7
Figure 11. SDA/SCL Levels
Figure 12. I
8
CA
CA
CA
CA
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Vcc
Vil
0V
Vih
ACK
9 10
First Data Byte (C1 or FM)
11 12 13
FM
FM
C1
C1
2
C Bus Timing
CA = Chip Address
C0
C0
14
FL
FL
2
C Bus)
dead band
15
16 17 18
STO
STO
FM
C1
ACK
19
2
C bus ) is as follows.
FL
C0
Data
44
STO
STO
ACK
45
Stop