NH82801BA S L7UU Intel, NH82801BA S L7UU Datasheet - Page 402

• Manufacturer Part Number: NH82801BA S L7UU
• Manufacturer: Intel

Specifications of NH82801BA S L7UU

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
9.10.14
402
DEVTRAP_EN—Device Trap Enable Register
I/O Address:
Default Value
Lockable:
Power Well:
This register enables the individual trap ranges to generate an SMI# when the corresponding status
bit in the DEVACT_STS register is set. When a range is enabled, I/O cycles associated with that
range will not be forwarded to LPC or IDE.
15:13
11:10
Bit
9:6
12
5
4
3
2
1
0
Reserved
KBC_TRP_EN — R/W. KBC (60/64h).
0 = Disable
1 = Enable
Reserved
Reserved
LEG_IO_TRP_EN — R/W. Parallel Port, Serial Port 1, Serial Port 2, Floppy Disk controller.
0 = Disable
1 = Enable
Reserved
IDES1_TRP_EN — R/W. IDE Secondary Drive 1.
0 = Disable
1 = Enable
IDES0_TRP_EN — R/W. IDE Secondary Drive 0.
0 = Disable
1 = Enable
IDEP1_TRP_EN — R/W. IDE Primary Drive 1.
0 = Disable
1 = Enable
IDEP0_TRP_EN — R/W. IDE Primary Drive 0.
0 = Disable
1 = Enable
PMBASE +48h
0000h
No
Core
Intel
Description
Attribute:
Size:
Usage:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
16-bit
Legacy Only