NH82801BA S L7UU Intel, NH82801BA S L7UU Datasheet - Page 577

• Manufacturer Part Number: NH82801BA S L7UU
• Manufacturer: Intel

Specifications of NH82801BA S L7UU

• Lead Free Status / RoHS Status: Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Bit
4:3
15
14
13
12
10
11
9
8
7
6
5
2
1
0
Read Completion Status (RCS)
Software clears this bit by writing a 1 to it.
0 = A codec read completes normally.
1 = A codec read results in a time-out.
This bit is not affected by D3
Bit 3 of Slot 12 — RO. Display bit 3 of the most recent slot 12.
Bit 2 of Slot 12 — RO. Display bit 2 of the most recent slot 12.
Bit 1 of Slot 12 — RO. Display bit 1 of the most recent slot 12.
AC_SDIN1 Resume Interrupt (S1RI) — R/WC. This bit indicates that a resume event occurred on
AC_SDIN1. Software clears this bit by writing a 1 to it.
0 = Resume event did not occur.
1 = Resume event occurred.
This bit is not affected by D3
AC_SDIN0 Resume Interrupt (S0RI) — R/WC. This bit indicates that a resume event occurred on
AC_SDIN0. Software clears this bit by writing a 1 to it.
0 = Resume event did not occur.
1 = Resume event occurred.
This bit is not affected by D3
AC_SDIN1 Codec Ready (S1CR) — RO. This bit reflects the state of the codec ready bit in
AC_SDIN1. Bus masters ignore the condition of the codec ready bits, so software must check this bit
before starting the bus masters. Once the codec is “ready”, it must never go “not ready”
spontaneously.
0 = Not Ready.
1 = Ready.
AC_SDIN0 Codec Ready (S0CR) — RO. This bit reflects the state of the codec ready bit in
AC_SDIN 0. Bus masters ignore the condition of the codec ready bits, so software must check this
bit before starting the bus masters. Once the codec is “ready”, it must never go “not ready”
spontaneously.
0 = Not Ready.
1 = Ready.
Microphone In Interrupt (MINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the Mic in channel interrupts status bits has been set.
PCM Out Interrupt (POINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the PCM out channel interrupts status bits has been set.
PCM In Interrupt (PIINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the PCM in channel interrupts status bits has been set.
Reserved
Modem Out Interrupt (MOINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the modem out channel interrupts status bits has been set.
Modem In Interrupt (MIINT) — RO.
0 = When the specific status bit is cleared, this bit will be cleared.
1 = One of the modem in channel interrupts status bits has been set.
GPI Status Change Interrupt (GSCI) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit reflects the state of bit 0 in slot 12, and is set when bit 0 of slot 12 is set. This indicates
This bit is not affected by D3
that one of the GPI’s changed state, and that the new values are available in slot 12.
HOT
HOT
HOT
HOT
to D0 Reset.
to D0 Reset.
to D0 Reset.
to D0 Reset.
—
R/WC. This bit indicates the status of codec read completions.
AC ’97 Modem Controller Registers (D31:F6)
Description
577