CY7C63722CXC Cypress Semiconductor Corp, CY7C63722CXC Datasheet
CY7C63722CXC
Specifications of CY7C63722CXC
Related parts for CY7C63722CXC
CY7C63722CXC Summary of contents
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... Each GPIO pin supports high-impedance inputs, internal ❐ pull-ups, open drain outputs or traditional CMOS outputs Maskable interrupts on all I/O pins ❐ Cypress Semiconductor Corporation Document #: 38-08022 Rev. *D enCoRe™ USB Combination Low-Speed USB and PS/2 Peripheral Controller SPI serial communication block ■ ...
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Logic Block Diagram XTALIN/P2.1 Xtal Internal Oscillator Oscillator 8-bit EPROM RISC 8K Byte Core Brown-out Reset Watch Dog Timer Low Voltage Reset Functional Overview enCoRe USB—The New USB Standard Cypress has reinvented its leadership position in the low-speed USB market ...
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The four capture timers save a programmable 8 bit range of the free-running timer when a GPIO edge occurs on the two capture pins (P0.0, P0.1). The CY7C637xxC includes an integrated USB serial interface ...
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Programming Model Refer to the CYASM Assembler User’s Guide for more details on firmware operation with the CY7C637xxC microcontrollers. Program Counter (PC) The 14-bit program counter (PC) allows access for Kbytes of EPROM using the CY7C637xxC architecture. ...
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MOV A,DSPINIT ■ Direct “Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction example, consider an instruction ...
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MNEMONIC Operand Opcode MOV A,[expr] direct 1A MOV A,[X+expr] index 1B MOV X,expr data 1C MOV X,[expr] direct 1D reserved 1E XPAGE 1F MOV A,X 40 MOV X,A 41 MOV PSP,A 60 CALL addr JMP addr 80-8F ...
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Memory Organization [1] Program Memory Organization After reset 14 -bit PC Figure 1. Program Memory Space with Interrupt Vector Table Note 1. The upper 32 bytes of the 8K PROM are reserved. Therefore, the user’s program must not overwrite this ...
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Data Memory Organization The CY7C637xxC microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below. After reset 8-bit DSP 8-bit ...
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Table 1. I/O Register Summary (continued) Register Name I/O Address USB Device Address 0x10 EP0 Counter Register 0x11 EP0 Mode Register 0x12 EP1 Counter Register 0x13 EP1 Mode Register 0x14 EP2 Counter Register 0x15 EP2 Mode Register 0x16 USB Status ...
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Clocking The chip can be clocked from either the internal on-chip clock, or from an oscillator based on an external resonator/crystal, as shown in Figure . No additional capacitance is included on chip at the XTALIN/OUT pins. Operation is controlled ...
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Bit 3: Low-voltage Reset Disable When V drops below V (see Section for the value of CC LVR V ) and the Low-voltage Reset circuit is enabled, the micro- LVR controller enters a partial suspend state for a period of ...
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Brown-out Reset bit) and 6 (Watchdog Reset bit) are used to record the occurrence of LVR/BOR and WDR respectively. The firmware can interrogate these bits to determine the cause of a reset. The microcontroller begins execution from ROM address 0x0000 ...
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Suspend Mode The CY7C637xxC parts support a versatile low-power suspend mode. In suspend mode, only an enabled interrupt or a LOW state on the D–/SDATA pin will wake the part. Two options are available. For lowest power, all internal circuits ...
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Table 2. Wake-up Timer Adjust Settings Adjust Bits [2:0] (Bits [6:4] in Figure ) 000 (reset state) 001 010 011 100 101 110 111 See Switching Characteristics on page 43 t WAKE General Purpose I/O Ports Ports 0 and 1 ...
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Figure 7. Port 0 Data (Address 0x00) Bit # Bit Name P0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Reset Bit [7:0]: P0[7: Port Pin is logic HIGH ...
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High Sink Mode (Mode1 = 1, Mode0 = 1, and the pin’s Data ■ Register = 0) Q1 and Q3 are OFF ON. The GPIO pin is capable of sinking current. High Drive Mode (Mode1 ...
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USB Enumeration A typical USB enumeration sequence is shown below. In this description, ‘Firmware’ refers to embedded firmware in the CY7C637xxC controller. 1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting ...
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Table 4. Control Modes to Force D+/D– Outputs D+/D– Control Action Forcing Bit [2:0] 000 Not forcing (SIE controls driver) 001 Force K (D+ HIGH, D– LOW) 010 Force J (D+ LOW, D– HIGH) 011 Force SE0 (D– LOW, D+ ...
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Bit 5: OUT Received valid OUT packet has been received. This bit is updated to ‘1’ after the last received packet in an OUT transaction. This bit is cleared by any non-locked writes to the register. 0 ...
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Bit [5:4]: Reserved Bit [3:0]: Byte Count Bit [3:0] Byte Count Bits indicate the number of data bytes in a trans- action: For IN transactions, firmware loads the count with the number of bytes to be transmitted to the host ...
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Figure 19. Diagram of USB-PS/2 System Connections Port 2.0 VREG Enable Port 2.5 Document #: 38-08022 Rev. *D 200Ω 3.3V Regulator V CC PS/2 Pull-up Enable 5 kΩ 5 kΩ USB - PS/2 Driver Port 2.4 On-chip CY7C63722C CY7C63723C CY7C63743C ...
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Serial Peripheral Interface (SPI) SPI is a four-wire, full-duplex serial communication interface between a master device and one or more slave devices. The CY7C637xxC SPI circuit supports byte serial transfers in either Master or Slave modes. The block diagram of ...
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Master SCK Selection The Master’s SCK is programmable to one of four clock settings, as shown in Figure 20. The frequency is selected with the Clock Select Bits of the SPI control register. The hardware provides 8 output clocks on ...
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SCK (CPOL = 0) SCK (CPOL = 1) SS CPHA = 0: x MSB MOSI/MISO Data Capture Strobe Interrupt Issued CPHA = 1: MSB MOSI/MISO Data Capture Strobe Interrupt Issued SPI Interrupt For SPI, an interrupt request is generated after ...
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Free-running Timer The 12-bit timer operates with a 1-μs tick, provides two interrupts (128-μs and 1.024-ms) and allows the firmware to directly time events that are duration. The lower eight bits of the timer ...
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Timer Capture Registers Four 8-bit capture timer registers provide both rising- and falling-edge event timing capture on two pins. Capture Timer A is connected to Pin 0.0, and Capture Timer B is connected to Pin 0.1. These can be used ...
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The four Capture Timer Data Registers are read-only, and are shown in Figure through Figure 30. Out of the 12-bit free running timer, the 8-bit captured in the Capture Timer Data Registers are determined by the Prescale Bit [2:0] in ...
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Bit 7: First Edge Hold 1 = The time of the first occurrence of an edge is held in the Capture Timer Data Register until the data is read. Subse- quent edges are ignored until the Capture Timer Data Regis- ...
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Processor Status and Control Register Figure 33. Processor Status and Control Register (Address 0xFF) Bit # 7 6 Bit Name IRQ Watchdog Pending Reset Read/Write R R/W Reset 0 1 Bit 7: IRQ Pending When an interrupt is generated, it ...
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During power-up, or during a low-voltage reset, the Processor Status and Control Register is set to 00010001, which indicates a LVR/BOR (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). Note that during the t ms ...
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Interrupt Sources The following sections provide details on the different types of interrupt sources. Figure 34. Global Interrupt Enable Register (Address 0x20) Bit # 7 6 Bit Name Wake-up GPIO Interrupt Interrupt Enable Enable Read/Write R/W R/W Reset 0 0 ...
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Bit 0: USB Bus Reset - PS/2 Interrupt Enable The function of this interrupt is selectable between detection of either a USB bus reset condition, or PS/2 activity. The se- lection is made with the USB-PS/2 Interrupt Mode bit in ...
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Figure 36. Interrupt Controller Logic Block Diagram CLR Enable [0] USB- (Reg 0x20) CLK PS/2 Int CLR Enable [2] (Reg 0x21) EP2 CLK Int CLR Enable [7] (Reg 0x20) Wake-up CLK ...
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Figure 40. Port 1 Interrupt Polarity Register (Address 0x07) Bit # Bit Name P1 Interrupt Polarity Read/Write Reset Port Bit Interrupt Polarity Register M U ...
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USB Mode Tables The following tables give details on mode setting for the USB Serial Interface Engine (SIE) for both the control endpoint (EP0) and non-control endpoints (EP1 and EP2). Table 8. USB Register Mode Encoding for Control and Non-Control ...
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NAK IN-Status OUT mode (1110) after ACKing a valid status stage OUT token. The firmware needs to update the mode for the SIE to respond appropriately. See Table 8 on what modes will be changed by the SIE. ...
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The response of the SIE can be summarized as follows: 1. The SIE will only respond to valid transactions, and will ignore non-valid ones. 2. The SIE will generate an interrupt when a valid transaction is completed or when the ...
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Table 10. Details of Modes for Differing Traffic Conditions (continued NAK OUT/Status IN < OUT 10 UC valid OUT > ...
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Table 10. Details of Modes for Differing Traffic Conditions (continued) OUT Endpoint ACK OUT, STALL Bit = 0 (Figure ) < OUT 10 data valid OUT > 10 junk ...
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Register Summary Address Register Name Bit 7 0x00 Port 0 Data 0x01 Port 1 Data 0x02 Port 2 Data Reserved 0x0A GPIO Port 0 Mode 0 0x0B GPIO Port 0 Mode 1 0x0C GPIO Port 1 Mode 0 0x0D GPIO ...
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Absolute Maximum Ratings Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied...... –0°C to +70°C Supply Voltage on V Relative to V ..........–0.5V to +7. Input Voltage .................................. –0. Voltage Applied to ...
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DC Characteristics FOSC = 6 MHz; Operating Temperature = 0 to 70°C (continued) Parameter V Static Output Low OLU V Static Output High, idle or suspend OHZ V Differential Input Sensitivity DI V Differential Input Common Mode Range CM V ...
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Switching Characteristics Parameter Description Internal Clock Mode Internal Clock Frequency F ICLK F Internal Clock Frequency, USB ICLK2 mode External Oscillator Mode T Input Clock Cycle Time CYC T Clock HIGH Time CH T Clock LOW Time CL Reset Timing ...
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Switching Characteristics (continued) Parameter Description T SPI Clock High Time SCKH T SPI Clock Low Time SCKL T Master Data Output Time MDO T Master Data Output Time, MDO1 First bit with CPHA = 1 T Master Input Data Set-up ...
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T PERIOD Differential Data Lines Figure 45. Differential to EOP Transition Skew and EOP Width T PERIOD Crossover Differential Data Lines PERIOD Differential Data Lines Document #: 38-08022 Rev. *D Figure 44. Receiver Jitter Tolerance T ...
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SS SCK (CPOL=0) T SCKH SCK (CPOL=1) T MDO MOSI MISO MSB T MSU SS T SSS SCK (CPOL=0) T SCKH SCK (CPOL=1) MOSI MSB T T SSU SDO MISO Document #: 38-08022 Rev. *D Figure 47. SPI Master Timing, ...
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SS SCK (CPOL=0) T SCKH SCK (CPOL=1) T MDO1 MOSI MSB MISO MSB T T MHD MSU SS T SSS SCK (CPOL=0) T SCKH SCK (CPOL=1) MSB MOSI T T SSU SHD T SDO1 MISO MSB Document #: 38-08022 Rev. ...
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Ordering Information Ordering Code EPROM Size CY7C63723C-PXC 8 KB CY7C63723C-SXC 8 KB CY7C63743C-PXC 8 KB CY7C63743C-SXC 8 KB CY7C63743C-QXC 8 KB CY7C63722C- Package Diagrams Document #: 38-08022 Rev. *D Package Package Type Name P3 18-Pin (300-Mil) Lead-free PDIP ...
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Figure 53. 24-Pin SOIC (.615 X .300 X .0932 Inches Document #: 38-08022 Rev. *D Figure 52. 18L SOIC .463 X.300 X .0932 Inches CY7C63722C CY7C63723C CY7C63743C 51-85023 *C 51-85025 *D Page [+] Feedback ...
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Document #: 38-08022 Rev. *D Figure 54. 24-Pin PDIP 1.260 X .270 X .140 I Figure 55. 24-Pin QSOP 8.65 X 3.9 X 1.44 MM CY7C63722C CY7C63723C CY7C63743C 51-85013 *C 51-85055 *C Page [+] Feedback ...
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Die Step: 1907 x 3011 microns Die Size: 1830.8 x 2909 microns Die Thickness: 14 mils = 355.6 microns Pad Size microns Table 11 below shows the die pad coordinates for the CY7C63722C-XC. The center location of ...
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Document History Page Document Title: CY7C63722C, CY7C63723C, CY7C63743C enCoRe™ USB Combination Low-Speed USB and PS/2 Peripheral Controller Document Number: 38-08022 Orig. of REV. ECN NO. Issue Date Change ** 118643 10/22/02 BON *A 243308 SEE ECN KKU *B 267229 See ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...