CY7C63722CXC Cypress Semiconductor Corp, CY7C63722CXC Datasheet - Page 15

• Manufacturer Part Number: CY7C63722CXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63722CXC

• Lead Free Status / RoHS Status: Not Compliant

Figure 7. Port 0 Data (Address 0x00)
Bit [7:0]: P0[7:0]
Figure 8. Port 1 Data (Address 0x01)
Bit [7:0]: P1[7:0]
Figure 9. GPIO Port 0 Mode0 Register (Address 0x0A)
Bit [7:0]: P0[7:0] Mode 0
Figure 10. GPIO Port 0 Mode1 Register (Address 0x0B)
Document #: 38-08022 Rev. *D
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Read/Write
Read/Write
Bit Name
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
Bit Name
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
1 = Port 0 Mode 0 is logic HIGH
0 = Port 0 Mode 0 is logic LOW
Bit Name
Bit Name
Notes
Reset
Reset
Reset
Reset
Bit #
Bit #
Bit #
Bit #
W
W
7
0
7
0
7
0
7
0
Pins 7:2 only in CY7C63743C
W
W
6
0
6
0
6
0
6
0
W
W
5
0
5
0
5
0
5
0
P0[7:0] Mode0
P0[7:0] Mode1
W
W
4
0
4
0
4
0
4
0
P0
P1
W
W
3
0
3
0
3
0
3
0
W
W
2
0
2
0
2
0
2
0
Pins 1:0 in
W
W
all parts
1
1
0
1
0
0
1
0
W
W
0
0
0
0
0
0
0
0
Bit [7:0]: P0[7:0] Mode 1
Figure 11. GPIO Port 1 Mode0 Register (Address 0x0C)
Bit [7:0]: P1[7:0] Mode 0
Figure 12. GPIO Port 1 Mode1 Register (Address 0x0D)
Bit [7:0]: P1[7:0] Mode 1
Each pin can be independently configured as high-impedance
inputs, inputs with internal pull-ups, open drain outputs, or tradi-
tional CMOS outputs with selectable drive strengths.
The driving state of each GPIO pin is determined by the value
written to the pin’s Data Register and by its associated Mode0
and Mode1 bits. Table 3 lists the configuration states based on
these bits. The GPIO ports default on reset to all Data and Mode
Registers cleared, so the pins are all in a high-impedance state.
The available GPIO output drive strength are:
■
■
■
Hi-Z Mode (Mode1 = 0 and Mode0 = 0)
Low Sink Mode (Mode1 = 1, Mode0 = 0, and the pin’s Data
Register = 0)
Medium Sink Mode (Mode1 = 0, Mode0 = 1, and the pin’s Data
Register = 0)
Read/Write
Read/Write
1 = Port Pin Mode 1 is logic HIGH
0 = Port Pin Mode 1 is logic LOW
1 = Port Pin Mode 0 is logic HIGH
0 = Port Pin Mode 0 is logic LOW
1 = Port Pin Mode 1 is logic HIGH
0 = Port Pin Mode 1 is logic LOW
Q1, Q2, and Q3 (Figure ) are OFF. The GPIO pin is not driven
internally. Performing a read from the Port Data Register re-
turn the actual logic value on the port pins.
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 2 mA of current.
Q1 and Q3 are OFF. Q2 is ON. The GPIO pin is capable of
sinking 8 mA of current.
Bit Name
Bit Name
Reset
Reset
Bit #
Bit #
W
W
7
0
7
0
W
W
6
0
6
0
W
W
5
0
5
0
P1[7:0] Mode0
P1[7:0] Mode1
W
W
4
0
4
0
W
W
3
0
3
0
CY7C63722C
CY7C63723C
CY7C63743C
W
W
2
0
2
0
Page 15 of 53
W
W
1
0
1
0
W
W
0
0
0
0
[+] Feedback