LH79524N0F100A1 NXP Semiconductors, LH79524N0F100A1 Datasheet - Page 31

• Manufacturer Part Number: LH79524N0F100A1
• Description: Microcontrollers (MCU) LCD USB ETH'NET MMU LFBGA208
• Manufacturer: NXP Semiconductors

Specifications of LH79524N0F100A1

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: Embedded Control
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.7/3V
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.9/3.6V
• Package Type: LFBGA
• Screening Level: Industrial
• Pin Count: 208
• Mounting: Surface Mount
• Rad Hardened: No
• Data Bus Width: 32 bit
• Program Memory Type: ROMLess
• Data Ram Size: 16 KB
• Interface Type: I2C, I2S, IrDA, SSP, UART, USB
• Maximum Clock Frequency: 76.205 MHz
• Number Of Programmable I/os: 108
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LFBGA
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Compliant

System-on-Chip
Product data sheet
nWE
SDCKE
DQM[3:0]
nSDCS[1:0]
SDCLK
SSPFRM
SSPTX
SSPRX
ETHERTXER
ETHERTX[3:0] Output 50 pF
ETHERTXEN
ETHERRXDV
ETHERRX[3:0]
SIGNAL
Output 30 pF
Output 30 pF
Output 30 pF
Output 30 pF
Output 30 pF
Output 50 pF tOVSSPFRM
Output 50 pF
Output 50 pF
Output 50 pF
TYPE LOAD
Input
Input
Input
tOVSSPTX
tOVTXER
tOHTXER
tOVTXEN
tOHTXEN
SYMBOL
tOHSDW
tOVSDW
tISRXDV
tIHRXDV
tISSPRX
tOVTXD
tOHTXD
Table 14. AC Signal Characteristics (Cont’d)
tSDCLK
tISRXD
tIHRXD
tOVDQ
tOHDQ
tOHSC
tOHC0
tOVSC
tOVC0
ETHERNET MAC CONTROLLER (EMC)
SYNCHRONOUS SERIAL PORT (SSP)
Rev. 02 — 17 March 2009
NXP Semiconductors
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
ETHERTXCLK/2 +
ETHERTXCLK/2 +
ETHERTXCLK/2 +
19.37 ns
2.0 ns
2.0 ns
2.0 ns
20 ns
10 ns
10 ns
10 ns
10 ns
MIN.
tSDCLK/2 + 4.5 ns
tSDCLK/2 + 4.5 ns
tSDCLK/2 + 5.0 ns
tSDCLK/2 + 4.5 ns
MAX.
14 ns
14 ns
25 ns
25 ns
25 ns
SDWE Write Enable Valid
SDWE Write Enable Hold
SDCKE Clock Enable Valid
SDCKE Clock Enable Hold
DQM Data Mask Valid
DQM Data Mask Hold
SDCS Data Mask Valid
SDCS Data Mask Hold
SDRAM Clock Period
tOVSSPFRM Output Valid,
Referenced to SSPCLK
SSP Transmit Valid
SSP Receive Setup
Transmit Data Valid after
ETHERTXCLK
Transmit Data Hold after
ETHERTXCLK
Transmit Data Valid after
ETHERTXCLK
Transmit Data Hold after
ETHERTXCLK
Transmit Data Valid after
ETHERTXCLK
Transmit Data Hold after
ETHERTXCLK
Receive Data Setup prior to
ETHERRXCLK
Receive Data Hold prior to
ETHERRXCLK
Receive Data Setup prior to
ETHERRXCLK
Receive Data Hold prior to
ETHERRXCLK
DESCRIPTION
LH79524/LH79525
31