LH79524N0F100A1 NXP Semiconductors, LH79524N0F100A1 Datasheet - Page 34

• Manufacturer Part Number: LH79524N0F100A1
• Description: Microcontrollers (MCU) LCD USB ETH'NET MMU LFBGA208
• Manufacturer: NXP Semiconductors

Specifications of LH79524N0F100A1

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: Embedded Control
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.7/3V
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.9/3.6V
• Package Type: LFBGA
• Screening Level: Industrial
• Pin Count: 208
• Mounting: Surface Mount
• Rad Hardened: No
• Data Bus Width: 32 bit
• Program Memory Type: ROMLess
• Data Ram Size: 16 KB
• Interface Type: I2C, I2S, IrDA, SSP, UART, USB
• Maximum Clock Frequency: 76.205 MHz
• Number Of Programmable I/os: 108
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LFBGA
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Lead Free Status / RoHS Status: Compliant

LH79524/LH79525
External Memory Controller Waveforms
transactions with both static and dynamic memory.
STATIC MEMORY WAVEFORMS
waveforms. Each wait state is one HCLK period.
nWAIT Input
nWAIT input that can be used by an external device to
extend the wait time during a memory access. The
SMC samples nWAIT at the beginning of at the begin-
ning of each system clock cycle. The system clock
cycle in which the nCSx signal is asserted counts as
the first wait state. See Figure 11 through Figure 20.
Read and Write Waveforms
states. As shown in the figure, SWAITOENx and
SWAITRDx are programmed to 0 for minimum Read
cycle time.
that the read occurs with zero wait states, on the first
rising edge following Address Valid. After a small prop-
agation delay, nOE is deasserted (as is nCSx), latching
the data into the SoC. The address line is held valid
one more HCLK period (‘C’ in the figure). Thus, the
minimum Read cycle is two HCLK periods.
both SWAITWRx and SWAITWENx programmed to
zero. The write access time is determined by the number
of wait states programmed in the SWAITWRx register.
34
The External Memory Controller (EMC) handles
This section illustrates static memory transaction
The EMC’s Static Memory Controller supports an
Figure 17 shows the Read cycle with zero wait
The zero programmed into the SWAITRDx indicates
Figure 18 shows the minimum write cycle time with
Rev. 02 — 17 March 2009
NXP Semiconductors
a small propagation delay) with Valid Address. Data
becomes valid another small propagation delay later.
Unlike Read transactions, nWE (or nBLEx) assertion is
always delayed one HCLK cycle. The nBLEx signal has
the same timing as nWE for write to 8-bit devices that
use the byte lane enables instead of the write enables.
HCLK cycle when the nWE (or nBLEx) signal is deas-
serted and the data is latched into the external memory
device. Valid address is held for one additional cycle
before deassertion (‘C’ in the figure), as is the Chip
Select. The minimum Write cycle is three HCLK periods.
register. Figure 19 shows the results of programming
SWAITRDx to 0x3, setting the EMC for three wait
states. The deassertion of nOE is delayed from the first
rising HCLK edge following Valid Address, as in Figure
17, to the fourth rising edge, a delay of 3 HCLK periods.
SWAITWRx and SWAITWENx registers for two Write
wait states: register SWAITWENx = 0x0, and SWAIT-
WRx = 0x2. Assertion of nCSx precedes nWE (nBLEx)
by one HCLK period. Then, instead of the nWE
(nBLEx) signal deasserting one HCLK period after
assertion, it is delayed two wait states and the signal
deasserts on the rising edge following two wait states.
descriptions and additional programming examples.
In Figure 18, nCSx is asserted coincident (following
The nWE (or nBLEx) signal remains asserted for one
Read wait state programming uses the SWAITRDx
Figure 20 shows the results of programming the
Chapter 7 of the User’s Guide has detailed register
Product data sheet
System-on-Chip