PPC440EP-3JC333C Applied Micro Circuits Corporation, PPC440EP-3JC333C Datasheet - Page 51

• Manufacturer Part Number: PPC440EP-3JC333C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EP-3JC333C

• Family Name: 440EP
• Device Core: PowerPC
• Device Core Size: 16b
• Frequency (max): 333MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 90C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: E-PBGA
• Lead Free Status / RoHS Status: Compliant

Multimode Signals
In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin
has multiple signal names assigned to distinguish different modes of operation, all of the names are shown.
Strapping Pins
One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only
during reset and are used for other functions during normal operation (see “Strapping” on page 84). Note that
these are not multiplexed pins since the function of the pins is not programmable.
Unused I/Os
Termination of unused receivers is generally required; however there are some exceptions that reduce or eliminate
the need for termination.
Signals Multiplexed with GPIO:
By Default after reset, signals shared with GPIO pins are configured as GPIO receivers. Termination however is not needed if
the GPIO during initialization are configured as outputs. To configure as drivers, set and clear the appropriate bits in the
GPIOx_ODR, GPIOx_TCR and GPIOx_OR registers as described in the GPIO chapter of the user’s manual.
PCI:
When the PCI bridge is unused, configure the PCI controller to park on the bus by pulling the PCIReq0 [Gnt] signal low. Parking
forces the PLB3 to PCI bridge to actively drive PCIAD31:0 and PCIC3:0[BE3:0]. The remaining PCI control signals must be
terminated as follows:
DDR:
When ECC is not used, no termination is needed for unused ECC signals (ECC0:7, DM8, and DS8).
USB Host:
When the USB Host interface is not used, a clock is still required for USB1Clk in order to reset the USB Host. If the USB Host
does not reset, it can interfere with the internal PLB3 and OPB buses. The USB Host signals must be terminated as follows:
USB Device:
The USB Device requires a subset of the USB signals to be terminated.
SMII0, RMII0 or MII:
SMII1, RMII1 or MII:
AMCC Proprietary
440EP – PPC440EP Embedded Processor
– Disable the internal PCI arbiter and enable PCI synchronous mode (See IIC Boot Strap Chapter in the user’s manual).
– Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through
– Terminate PCIReq1:5 through
– Terminate PCIReq0[Gnt] through a
– A clock must be connected to USB1Clk. The clock can be any frequency from 32kHz to 48MHz.
– USB1HostXcvr and USB1HostXcv signals must be pulled down.
– USB2LS0[Drvrlnh1][RejectPkt] must be pulled by unless used as a packet reject input.
– USB2D10:7, USB1DevXcvr, USB1DevXcvr and USB2Clk signals must be pulled down.
– Configure EMAC0 to use internal clocks by setting SDR0_MFR[E0CS]=1 and reset EMAC0 by setting
– No pull ups or pull downs required
– Configure EMAC1 to use internal clocks by setting SDR0_MFR[E1CS]=1 and reset EMAC1 by setting
– No pull ups or downs required.
(Note: Synchronous mode is not supported when operating the PCI bus. This mode should only be used for
terminating an unused PCI interface).
EMAC0_MR0[SRST]=1.
EMAC0_MR1[SRST]=1.
3k
Ω resistors to +3.3v.
1k
Ω resistor to GND.
3k
Ω resistors to +3.3v.
Revision 1.29 – May 07, 2008
Data Sheet
51