PPC440EP-3JC333C Applied Micro Circuits Corporation, PPC440EP-3JC333C Datasheet - Page 84

• Manufacturer Part Number: PPC440EP-3JC333C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EP-3JC333C

• Family Name: 440EP
• Device Core: PowerPC
• Device Core Size: 16b
• Frequency (max): 333MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.4/2.3V
• Operating Temp Range: -40C to 90C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: E-PBGA
• Lead Free Status / RoHS Status: Compliant

Initialization
The PPC440EP provides the option for setting initial parameters based on default values or by reading them from
a slave PROM attached to the IIC0 bus (see “EEPROM” below). Some of the default values can be altered by
strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440EP start-up. The actual capture instant is the nearest reference clock edge before
the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)
resistors to select the desired default conditions. These pins are used for strap functions only during reset.
Following reset they are used for normal functions. The signal names assigned to the pins for normal operation are
shown in parentheses following the pin number.
To isolate the strapping pins, the ExtReset signal may be used as a buffer enable or multiplexer select.
The following table lists the strapping pins along with their functions and strapping options:
EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device
connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440EP
sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,
SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly.
The initialization settings and their default values are covered in detail in the PowerPC 440EP User’s Manual.
84
Table 26. Strapping Pin Assignments
Revision 1.29 – May 07, 2008
Serial device is disabled. Each of the six options (A–
F) is a combination of boot source, boot-source
width, and clock frequency specifications. Refer to
the IIC Bootstrap Controller chapter in the
PPC440EP Embedded Processor User’s Manual for
details.
Serial device is enabled. The option being selected is
the IIC0 slave address that will respond with
configuration data.
Note: If reading of configuration data from the serial
device fails, the PPC440EP defaults to configuration
X.
Data Sheet
Function
G (0xA8)
H (0xA4)
Option
A
B
C
D
E
F
440EP – PPC440EP Embedded Processor
(UART0_DCD)
R25
0
0
0
0
1
1
1
1
Ball Strapping
(UART0_DSR)
U26
0
0
1
1
0
1
0
1
AMCC Proprietary
(UART0_CTS)
V26
0
1
0
1
0
0
1
1