MCIMX257DJM4A Freescale, MCIMX257DJM4A Datasheet - Page 102

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MCIMX257DJM4A

Manufacturer Part Number
MCIMX257DJM4A
Description
Manufacturer
Freescale
Datasheet

Specifications of MCIMX257DJM4A

Operating Temperature (min)
-20C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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1
2
102
In cases where SDMA TAP is put in the chain, the maximum TCK frequency is limited by the maximum ratio of 1:8 of SDMA
core frequency to TCK. This implies a maximum frequency of 8.25 MHz (or 121.2 ns) for a 66 MHz IPG clock.
V
SJ10
SJ11
SJ12
SJ13
SJ1
SJ2
SJ3
SJ4
SJ5
SJ6
SJ7
SJ8
SJ9
M –
ID
mid point voltage
(Input)
TCK cycle time
TCK clock pulse width measured at
TCK rise and fall times
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO high impedance
TRST assert time
TRST set-up time to TCK low
TRST
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 6
(Input)
TCK
SJ12
Parameter
SJ13
Table 76. SJC Timing Parameters
Figure 75. TRST Timing Diagram
V
M
2
100
Min.
100
40
10
50
10
50
40
All Frequencies
1
Max.
50
50
44
44
3
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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