MC9328MX21VG Freescale, MC9328MX21VG Datasheet - Page 42

• Manufacturer Part Number: MC9328MX21VG
• Manufacturer: Freescale

Specifications of MC9328MX21VG

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Specifications
3.12.2
In SDIO, there is a 1-bit or 4-bit interrupt response from the SDIO peripheral card. In 1-bit mode, the
interrupt response is simply that the SD_DAT[1] line is held low. The SD_DAT[1] line is not used as data
in this mode. The memory controller generates an interrupt according to this low and the system interrupt
continues until the source is removed (SD_DAT[1] returns to its high level).
In 4-bit mode, the interrupt is less simple. The interrupt triggers at a particular period called the Interrupt
Period during the data access, and the controller must sample SD_DAT[1] during this short period to
determine the IRQ status of the attached card. The interrupt period only happens at the boundary of each
block (512 bytes).
ReadWait is another feature in SDIO that allows the user to submit commands during the data transfer. In
this mode, the block temporarily pauses the data transfer operation counter and related status, yet keeps
the clock running, and allows the user to submit commands as normal. After all commands are submitted,
the user can switch back to the data transfer operation and all counter and status values are resumed as
access continues.
42
Command read cycle
Command-command cycle
Command write cycle
Stop transmission cycle
TAAC: Data read access time -1 defined in CSD register bit[119:112]
NSAC: Data read access time -2 in CLK cycles (NSAC·100) defined in CSD register bit[111:104]
For 1-bit
For 4-bit
DAT[1]
DAT[1]
CMD
For 4-bit
For 4-bit
DAT[1]
DAT[2]
SDIO-IRQ and ReadWait Service Handling
CMD
S T
Parameter
Interrupt Period
S
S
Content
Table 28. Timing Values for
Block Data
Block Data
******
CRC
E Z Z
E
E Z Z P
Figure 32. SDIO ReadWait Timing Diagram
Z Z L H
Figure 31. SDIO IRQ Timing Diagram
L L L L L L L L L L L L L L L L L L L L L H Z S
MC9328MX21 Technical Data, Rev. 3.4
S
P S T
S
Symbol
Response
NWR
NRC
NCC
NST
Block Data
CMD52
Figure 26
Interrupt Period
E Z Z
L H
CRC
E
Minimum
Z
through
E Z Z
8
8
2
2
Z
IRQ
Figure 30
S
******
S
Block Data
Block Data
******
Maximum
(Continued)
Block Data
–
–
–
2
E
E
Freescale Semiconductor
E
Z
Z Z
Clock cycles
Clock cycles
Clock cycles
Clock cycles
IRQ
Unit