MC9328MX21VG Freescale, MC9328MX21VG Datasheet - Page 6

• Manufacturer Part Number: MC9328MX21VG
• Manufacturer: Freescale

Specifications of MC9328MX21VG

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Signal Descriptions
6
Signal Name
SDIBA [3:0]
BOOT [3:0]
SDBA [4:0]
DQM [3:0]
MA [11:0]
SDCKE0
SDCKE1
CS [5:0]
SDCLK
DTACK
SDWE
BCLK
CSD0
CSD1
ECB
RAS
CAS
EB1
EB2
EB3
LBA
RW
OE
Byte Strobe—Active low external enable byte signal that controls D [23:16], shared with SDRAM DQM1.
Byte Strobe—Active low external enable byte signal that controls D [15:8], shared with SDRAM DQM2
and PCMCIA PC_REG.
LSB Byte Strobe—Active low external enable byte signal that controls D [7:0], shared with SDRAM
DQM3 and PCMCIA PC_IORD.
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR.
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the
Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is
selected. DTACK is multiplexed with CS4.
Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-
going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by flash device causing the external burst device to latch the starting burst
address.
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is also
shared with the PCMCIA PC_WE.
DTACK signal—External input data acknowledge signal, multiplexed with CS4.
System Boot Mode Select—The operational system boot mode upon system reset is determined by the
settings of these pins. To hardwire these inputs low, terminate with a 1 KΩ resister to ground. For a logic
high, terminate with a 1 KΩ resistor to VDDA. Do not change the state of these inputs after power-up.
Boot 3 should always be tied to logic low.
SDRAM non-interleave mode bank address signals. These signals are multiplexed with address signals
A[20:16].
SDRAM interleave addressing mode bank address signals. These signals are multiplexed with address
signals A[24:21].
SDRAM address signals. MA[9:0] are multiplexed with address signals A[10:1].
SDRAM data qualifier mask multiplexed with EB[3:0]. DQM3 corresponds to D[31:24], DQM2
corresponds to D[23:16], DQM1 corresponds to D[15:8], and DQM0 corresponds to D[7:0].
SDRAM Chip Select signal. This signal is multiplexed with the CS2 signal. This signal is selectable by
programming the Function Multiplexing Control Register in the System Control chapter.
SDRAM Chip Select signal. This signal is multiplexed with the CS3 signal. This signal is selectable by
programming the Function Multiplexing Control Register in the System Control chapter.
SDRAM Row Address Select signal.
SDRAM Column Address Select signal
SDRAM Write Enable signal
SDRAM Clock Enable 0
SDRAM Clock Enable 1
SDRAM Clock
Table 2. i.MX21 Signal Descriptions (Continued)
MC9328MX21 Technical Data, Rev. 3.4
SDRAM Controller
Bootstrap
Function/Notes
Freescale Semiconductor