SC1200UFH-266BF 33 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266BF 33 Datasheet - Page 113

• Manufacturer Part Number: SC1200UFH-266BF 33
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266BF 33

• Lead Free Status / RoHS Status: Compliant

SuperI/O Module
AMD Geode™ SC1200/SC1201 Processor Data Book
Index 0Ch
Index 0Dh
Index Programmable
Index Programmable
Index Programmable
Bit
3:0
6:0
7:0
7:0
7:0
2
1
0
7
6
5
4
7
Description
Data Mode. This bit is reset at V
0: Enable BCD format.
1: Enable Binary format.
Hour Mode. This bit is reset at V
0: Enable 12-hour format.
1: Enable 24-hour format.
Daylight Saving. This bit is reset at V
0: Disable.
1: Enable:
IRQ Flag. Mirrors the value on the interrupt output signal. When interrupt is active, IRQF is 1. To clear this bit (and deacti-
vate the interrupt pin), read the CRC Register as the flag bits UF, AF and PF are cleared after reading this register.
0: IRQ inactive.
1: Logic equation is true: ((UIE and UF) or (AIE and AF) or (PIE and PF)).
Periodic Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition, this
bit is cleared to 0 when this register is read.
0: No transition occurred on the selected tap since the last read.
1: Transition occurred on the selected tap of the divider chain.
Alarm Interrupt Flag. Cleared to 0 as long as bit 7 of the CRD Register is reads 0. In addition, this bit is cleared to 0 when
this register is read.
0: No alarm detected since the last read.
1: Alarm condition detected.
Update Ended Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition,
this bit is cleared to 0 when this register is read.
0: No update occurred since the last read.
1: Time registers updated.
Reserved.
Valid RAM and Time. This bit senses the voltage that feeds the RTC (VSB or VBAT) and indicates whether or not it was too
low since the last time this bit was read. If it was too low, the RTC contents (time/calendar registers and CMOS RAM) is not
valid.
0: The voltage that feeds the RTC was too low.
1: RTC contents (time/calendar registers and CMOS RAM) are valid.
Reserved.
Date of Month Alarm Data. Values may be 01 to 31 in BCD format or 01 to 1F in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default)
Month Alarm Data. Values may be 01 to 12 in BCD format or 01 to 0C in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default)
Century Data. Values may be 00 to 99 in BCD format or 00 to 63 in Binary format.
- In the spring, time advances from1:59:59 AM to 3:00:00 AM on the first Sunday in April.
- In the fall, time returns from 1:59:59 AM to 1:00:00 AM on the last Sunday in October.
Table 5-20. RTC Registers (Continued)
Date of Month Alarm Register - DOMA (R/W)
PP
PP
Month Alarm Register - MONA (R/W)
RTC Control Register C - CRC (RO)
RTC Control Register D - CRD (RO)
power-up reset only.
power-up reset only.
Century Register - CEN (R/W)
PP
power-up reset only.
32579B
Reset Type: Bit Specific
Reset Type: V
Reset Type: V
Reset Type: V
Reset Type: V
PP
PP
PP
PP
PUR
PUR
PUR
PUR
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