SC1200UFH-266BF 33 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266BF 33 Datasheet - Page 97

• Manufacturer Part Number: SC1200UFH-266BF 33
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266BF 33

• Lead Free Status / RoHS Status: Compliant

SuperI/O Module
5.4.1
Table 5-4 lists the SIO Control and Configuration registers and Table 5-5 provides their bit formats.
AMD Geode™ SC1200/SC1201 Processor Data Book
Index 20h
Index 21h
Index 22h
Note:
Index 27h
Index
2Eh
20h
21h
22h
27h
Bit
7:0
7:6
4:2
6:4
3:2
7:0
7
1
0
5
1
0
This register is reset only when V
SIO Control and Configuration Registers
Description
Chip ID. Contains the identity number of the module. The SIO module is identified by the value F5h.
General Purpose Scratch. When bit 5 is set to 1, these bits are RO. After reset, these bits can be read or write. Once
changed to RO, the bits can be changed back to R/W only by a hardware reset.
Lock Scratch. This bit controls bits 7 and 6 of this register. Once this bit is set to 1 by software, it can be cleared to 0 only
by a hardware reset.
0: Bits 7 and 6 of this register are R/W bits. (Default)
1: Bits 7 and 6 of this register are RO bits.
Reserved.
SW Reset. Read always returns 0.
0: Ignored. (Default)
1: Resets all devices that are reset by MR (with the exception of the lock bits) and the registers of the SWC.
Global Device Enable. This bit controls the function enable of all the logical devices in the SIO module, except the SWC
and the RTC. It allows them to be disabled simultaneously by writing to a single bit.
0: All logical devices in the SIO module are disabled, except the SWC and the RTC.
1: Each logical device is enabled according to its Activate register at Index 30h. (Default)
Reserved.
General Purpose Scratch. Battery-backed.
Reserved.
Reserved.
Reserved. (RO)
SIO Revision ID. (RO) This RO register contains the identity number of the chip revision. SRID is incremented on each revi-
sion.
Type
R/W
R/W
RO
RO
---
Name
SID. SIO ID
SIOCF1. SIO Configuration 1
SIOCF2. SIO Configuration 2
SRID. SIO Revision ID
RSVD. Reserved exclusively for AMD use.
Table 5-4. SIO Control and Configuration Register Map
Table 5-5. SIO Control and Configuration Registers
SIO Configuration 2 Register - SIOCF2 (R/W)
SIO Configuration 1 Register - SIOCF1 (RW)
PP
is first applied.
SIO Revision ID Register - SRID (RO)
SIO ID Register - SID (RO)
Power Rail
32579B
V
V
V
V
CORE
CORE
CORE
---
PP
Reset Value: F5h
Reset Value: 01h
Reset Value: 02h
Reset Value: 01h
Reset Value
F5h
01h
02h
01h
---
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