AT94K10AL-25DQC Atmel, AT94K10AL-25DQC Datasheet - Page 68

• Manufacturer Part Number: AT94K10AL-25DQC
• Manufacturer: Atmel

Specifications of AT94K10AL-25DQC

• Device System Gates: 10000
• Propagation Delay Time: 12.7ns
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• Lead Free Status / RoHS Status: Not Compliant

• Bit 6 - OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the
data in OCR1A – Output Compare Register 1A. OCF1A is cleared by the hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a
logic 1 to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare Interrupt
Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is
executed.
• Bit 5 - OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the
data in OCR1B – Output Compare Register 1B. OCF1B is cleared by the hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a
logic 1 to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match Inter-
rupt Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is
executed.
• Bit 4 - TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by the
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is
cleared by writing a logic 1 to the flag. When the I-bit in SREG, and TOIE2 (Timer/Counter1
Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow Interrupt is
executed. In PWM mode, this bit is set when Timer/Counter2 advances from $00.
• Bit 3 - ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value
has been transferred to the input capture register – ICR1. ICF1 is cleared by the hardware when
executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a
logic 1 to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt
Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
• Bit 2 - OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and the data in
OCR2 – Output Compare Register 2. OCF2 is cleared by the hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic 1 to the
flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare Interrupt Enable), and the
OCF2 are set (one), the Timer/Counter2 Output Compare Interrupt is executed.
• Bit 1 - TOV0: Timer/Counter0 Overflow Flag
The TOV0 bit is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by the
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is
cleared by writing a logic 1 to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Over-
flow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is
executed. In PWM mode, this bit is set when Timer/Counter0 advances from $00.
• Bit 0 - OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and the data in
OCR0 – Output Compare Register 0. OCF0 is cleared by the hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic 1 to the
flag. When the I-bit in SREG, and OCIE0 (Timer/Counter2 Compare Interrupt Enable), and the
OCF0 are set (one), the Timer/Counter0 Output Compare Interrupt is executed.
AT94KAL Series FPSLIC
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1138I–FPSLI–1/08