SLATA128MM1UI STEC, SLATA128MM1UI Datasheet - Page 31

• Manufacturer Part Number: SLATA128MM1UI
• Manufacturer: STEC
• Type: PC Cardr

Specifications of SLATA128MM1UI

• Density: 128MByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: Not Required
• Mounting: Socket
• Pin Count: 68
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 3.18/4.75V
• Operating Supply Voltage (max): 3.465/5.25V
• Programmable: Yes
• Lead Free Status / RoHS Status: Compliant

SLATAxxx(M/G)M1U(I)
Datasheet
5.2
Data Register
Error Register
Sector Count Register
Sector Number Register
Cylinder Low Register
Cylinder High Register
Drive/Head Register
Status Register
Alternate Status Register
Device Control Register
Drive Address Register
Command Register
Task File Register
Task File Registers
The Data Register is a 16-bit read/write register used for transferring data
between the ATA PC Card and the host. This register can be accessed in word
mode and byte mode.
The Error Register is a read-only register that is used for analyzing an error. This
register is valid when the BSY bit in the Status register and Alternate Status
register are set to ―0‖ (Ready). Diagnostic Codes are returned in the Error
Register after a Execute Drive Diagnostic command (code 90h). Extended Error
Codes returned in the Error Register after a Request Sense command (code
03h).
This register contains the numbers of sectors of data requested to be transferred
on a read or write operation between the host and the ATA PC Card. If the value
in the register is 0, a count of 256 sectors is indicated.
When the LBA bit in the Drive/Head register is 0, this register contains the
starting sector number for any media access. When the LBA bit is set to 1, this
register contains bits 7:0 of the LBA for any media access.
In CHS mode (LBA=0), this register contains the low-order bits of the starting
cylinder address. In LBA mode, it contains bits 15:8 of the LBA.
In CHS mode (LBA=0), this register contains the high-order bits of the starting
cylinder address. In LBA mode, it contains bits 23:16 of the LBA.
This register selects the ATA PC Card address translation (CHS or LBA) and
provides head address (CHS) or high-order address bits 27:24 for LBA.
This read-only register indicates status of a command execution. When the BSY
bit is ―0‖, the other bits are valid; when the BSY bit is ―1‖, the other bits are not
valid. When the register is read, the interrupt pin, is cleared.
This register is the same as the Status register, except that is not negated when
the register is read.
This write-only register is used for controlling the interrupt request and issuing an
ATA soft reset to the ATA PC Card.
This read-only register is used for confirming the ATA PC Card’s status. This
register is provided for compatibility with the AT disk drive interface and it is not
recommended that this register be mapped into the host’s I/O space because of
potential conflicts on bit 7.
This write-only register is used for writing the command that executes the ATA
PC Card’s operation. The command code is written in the command register after
its parameters are written in the Task File during the ATA PC Card ready state.
Table 23: ATA PC Card Task File Registers
61000-04497-117, April 2008
Description
ATA PC Card
31