M48Z09-100PC1 STMicroelectronics, M48Z09-100PC1 Datasheet - Page 3

• Manufacturer Part Number: M48Z09-100PC1
• Manufacturer: STMicroelectronics
• Type: NVSRAMr

Specifications of M48Z09-100PC1

• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 100ns
• Operating Supply Voltage (typ): 5V
• Package Type: PCDIP
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 80mA
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 3. Block Diagram
READ MODE
The M48Z09,19 is in the Read Mode whenever W
(Write Enable) is high, E1 (Chip Enable 1) is low,
and E2 (Chip Enable 2) is high. The device archi-
tecture allows ripple- through access of data from
eight of 65,536 locations in the static storage array.
Thus, the unique address specified by the 13 Ad-
dress Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within t
Access Time) after the last address input signal is
stable, providing that the E1, E2, and G access
times are also satisfied. If the E1, E2 and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (t
or t
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are
activated before t
to an indeterminate state until t
Inputs are changed while E1, E2 and G remain
active, output data will remain valid for t
put Data Hold Time) but will go indeterminate until
the next Address Access.
E2HQV
) or Output Enable Access Time (t
LITHIUM
CELL
AVQV
, the data lines will be driven
VOLTAGE SENSE
V CC
AVQV
SWITCHING
CIRCUITRY
AND
. If the Address
AVQV
AXQX
INT
(Address
GLQV
E1LQV
(Out-
).
POWER
V PFD
AC MEASUREMENT CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note that Output Hi-Z is defined as the point where data
is no longer driven.
Figure 4. AC Testing Load Circuit
C L includes JIG capacitance
DEVICE
UNDER
TEST
SRAM ARRAY
8K x 8
V SS
1k
5V
M48Z09, M48Z19
1.8k
C L = 100pF or 30pF
A0-A12
DQ0-DQ7
E1
E2
W
G
0 to 3V
1.5V
AI01397
5ns
OUT
AI01398
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