IDT82V3280DQ IDT, Integrated Device Technology Inc, IDT82V3280DQ Datasheet - Page 59

• Manufacturer Part Number: IDT82V3280DQ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3280DQ

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP EP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 42: Register List and Map
7
ters are read or written via the microprocessor interface.
PROTECTION_CNFG is recommended to be confirmed to make sure
whether the write operation is enabled. The device provides 3 register
protection modes:
cleared by writing ‘1’.
2CH, 4EH, 4FH, 5AH, 5BH, 62H ~ 64H, 68H and 69H. The names of
shared registers are marked with a *. Before register read/write opera-
tion, register T4_T0_REG_SEL_CNFG is recommended to be con-
firmed to make sure whether the register operation is available for T0 or
T4 path.
Programming Information
IDT82V3280
Address
(Hex)
After reset, all the registers are set to their default values. The regis-
Before
Writing ‘0’ to the registers will take no effect if the registers are
T0 and T4 paths share some registers, whose addresses are 26H ~
0A
00
01
02
04
05
06
07
08
09
• Protected mode: no other registers can be written except register
• Fully Unprotected mode: all the writable registers can be written;
• Single Unprotected mode: one more register can be written
PROTECTION_CNFG itself;
besides register PROTECTION_CNFG. After write operation
(not including writing a ‘1’ to clear a bit to ‘0’), the device auto-
matically switches to Protected mode.
ID[7:0] - Device ID 1
ID[15:8] - Device ID 2
MPU_PIN_STS - MPU_MODE[2:0]
Pins Status
NOMINAL_FREQ[7:0]_CNFG - Crys-
tal Oscillator Frequency Offset Calibra-
tion Configuration 1
NOMINAL_FREQ[15:8]_CNFG - Crys-
tal Oscillator Frequency Offset Calibra-
tion Configuration 2
NOMINAL_FREQ[23:16]_CNFG
Crystal Oscillator Frequency Offset
Calibration Configuration 3
T4_T0_REG_SEL_CNFG - T0 / T4
Registers Selection Configuration
PHASE_ALARM_TIME_OUT_CNFG -
Phase Lock Alarm Time-Out Configu-
ration
INPUT_MODE_CNFG - Input Mode
Configuration
DIFFERENTIAL_IN_OUT_OSCI_CNF
G - Differential Input / Output Port &
Master Clock Configuration
PROGRAMMING INFORMATION
any
Register Name
write
operation,
the
-
AUTO_EX
T_SYNC_
MULTI_FACTOR[1:0]
Bit 7
EN
value
-
-
-
EXT_SYN
in
C_EN
Bit 6
-
-
-
Global Control Registers
register
PH_ALAR
M_TIMEO
Bit 5
UT
59
-
-
-
NOMINAL_FREQ_VALUE[23:16]
Single-word Registers. Take the registers (04H, 05H and 06H) for an
example, the write operation for the Multi-word Registers follows a fixed
sequence. The register (04H) is configured first and the register (06H) is
configured last. The three registers are configured continuously and
should not be interrupted by any operation. The crystal calibration con-
figuration will take effect after all the three registers are configured. Dur-
ing read operation, the register (04H) is read first and the register (06H)
is read last. The crystal calibration reading should be continuous and not
be interrupted by any operation.
Reserved. To ensure proper and predictable operation, bits designated
as Reserved should not be written by the users. In addition, their value
should be masked out from any testing or error detection methods that
are implemented.
7.1
of their addresses.
NOMINAL_FREQ_VALUE[15:8]
NOMINAL_FREQ_VALUE[7:0]
Table 42
The access of the Multi-word Registers is different from that of the
Certain bit locations within the device register map are designated as
T4_T0_SE
SYNC_FREQ[1:0]
Bit 4
L
-
-
ID[15:8]
ID[7:0]
REGISTER MAP
is the map of all the registers, sorted in an ascending order
TIME_OUT_VALUE[5:0]
Bit 3
-
-
-
IN_SONET
OSC_EDG
_SDH
Bit 2
E
-
MPU_PIN_STS[2:0]
MASTER_
OUT7_PE
CL_LVDS
SLAVE
Bit 1
-
REVERTIV
OUT6_PE
CL_LVDS
E_MODE
Bit 0
-
March 02, 2009
WAN PLL
Reference
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