MM74HC123AMTCX_NF40 Fairchild Semiconductor, MM74HC123AMTCX_NF40 Datasheet - Page 5

• Manufacturer Part Number: MM74HC123AMTCX_NF40
• Manufacturer: Fairchild Semiconductor

Specifications of MM74HC123AMTCX_NF40

• Logic Family: HC
• High Level Output Current: -5.2mA
• Low Level Output Current: 5.2mA
• Quiescent Current: 8nA
• Number Of Elements: 2
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Abs. Propagation Delay Time: 250ns
• Operating Supply Voltage (min): 2V
• Lead Free Status / RoHS Status: Compliant

Theory of Operation
Trigger Operation
As shown in Figure 1 and the logic diagram, before an
input trigger occurs, the one shot is in the quiescent state
with the Q output LOW, and the timing capacitor C
pletely charged to V
V
valid trigger is recognized, which turns on comparator C1
and Nchannel transistor N11. At the same time the output
latch is set. With transistor N1 on, the capacitor C
idly discharges toward GND until V
point the output of comparator C1 changes state and tran-
sistor N1 turns off. Comparator C1 then turns off while at
the same time comparator C2 turns on. With transistor N1
off, the capacitor C
resistor, R
equals V
output latch to reset (Q goes LOW) while at the same time
disabling comparator C2. This ends the timing cycle with
the monostable in the quiescent state, waiting for the next
trigger.
A valid trigger is also recognized when trigger input B goes
from GND to V
is at V
clear goes from GND to V
V
It should be noted that in the quiescent state C
charged to V
to be zero. Both comparators are “off” with the total device
current due only to reverse junction leakages. An added
feature of the MM74HC123A is that the output latch is set
via the input trigger without regard to the capacitor voltage.
Thus, propagation delay from trigger to Q is independent of
the value of C
waveform.
CC
CC
6).
to GND (while inputs B and clear are held to V
CC
2). The MM74HC123A can also be triggered when
REF2
EXT
CC
, toward V
, comparator C2 changes state causing the
CC
EXT
causing the current through resistor R
(while input A is at GND and input clear
, R
EXT
CC
EXT
. When the trigger input A goes from
begins to charge through the timing
CC
CC
, or the duty cycle of the input
. When the voltage across C
(while A is at GND and B is at
REF1
is reached. At this
EXT
EXT
EXT
is fully
CC
com-
rap-
EXT
EXT
FIGURE 1.
) a
5
Retrigger Operation
The MM74HC123A is retriggered if a valid trigger occurs 3
followed by another trigger 4 before the Q output has
returned to the quiescent (zero) state. Any retrigger, after
the timing node voltage at the R/C
from V
increase in output pulse width T. When a valid retrigger is
initiated 4, the voltage at the R/C
V
toward V
after the last valid retrigger.
Because the trigger-control circuit flip-flop resets shortly
after C
lower reference circuit, the minimum retrigger time, t
function of internal propagation delays and the discharge
time of C
Another removal/retrigger time occurs when a short clear
pulse is used. Upon receipt of a clear, the one shot must
charge the capacitor up to the upper trip point before the
one shot is ready to receive the next trigger. This time is
dependent on the capacitor used and is approximately:
REF1
REF1
before progressing along the RC charging curve
X
X
CC
has discharged to the reference voltage of the
:
, but has not yet reached V
. The Q output will remain HIGH until time T,
EXT
EXT
pin will again drop to
pin has begun to rise
REF2
www.fairchildsemi.com
, will cause an
rr
is a