LFEC10E-3F484C LATTICE SEMICONDUCTOR, LFEC10E-3F484C Datasheet - Page 25

• Manufacturer Part Number: LFEC10E-3F484C
• Description: FPGA LatticeEC Family 10200 Cells 340MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFEC10E-3F484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 10200
• Maximum Internal Frequency: 340 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 288
• Ram Bits: 282624
• In System Programmability: Yes

Lattice Semiconductor
Table 2-12. PIO Signal List
Figure 2-25. DQS Routing
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
CE0, CE1
CLK0, CLK1
LSR
GSRN
INCK
DQS
INDD
INFF
IPOS0, IPOS1
ONEG0
OPOS0,
OPOS1 ONEG1
TD
DDRCLKPOL
Name
Control from the core
Control from the core
Control from the core
Control from routing
Input to the core
Input to PIO
Input to the core
Input to the core
Input to the core
Control from the core
Control from the core
Tristate control from the core
Tristate control from the core
Control from clock polarity bus
DQS
Type
Clock enables for input and output block FFs.
System clocks for input and output blocks.
Local Set/Reset.
Global Set/Reset (active low).
Input to Primary Clock Network or PLL reference inputs.
DQS signal from logic (routing) to PIO.
Unregistered data input to core.
Registered input on positive edge of the clock (CLK0).
DDRX registered inputs to the core.
Output signals from the core for SDR and DDR operation.
Output signals from the core for DDR operation
Signals to Tristate Register block for DDR operation.
Tristate signal from the core used in SDR operation.
Controls the polarity of the clock (CLK0) that feed the DDR input block.
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
2-22
Buffer
Delay
sysIO
LatticeECP/EC Family Data Sheet
Description
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
DQS Pin
PADA "T"
PADB "C"
Assigned
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
Architecture