LFX125EB-04F256I LATTICE SEMICONDUCTOR, LFX125EB-04F256I Datasheet - Page 23

• Manufacturer Part Number: LFX125EB-04F256I
• Description: FPGA ispXPGA® Family 139K Gates 1936 Cells EECMOS Technology 2.5V/3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFX125EB-04F256I

• Package: 256FBGA
• Family Name: ispXPGA®
• Device Logic Units: 1936
• Device System Gates: 139000
• Number Of Registers: 3800
• Typical Operating Supply Voltage: 2.5|3.3 V
• Maximum Number Of User I/os: 160
• Ram Bits: 94208
• Re-programmability Support: Yes

Lattice Semiconductor
Configuration and Programming
The ispXPGA family of devices takes a unique approach to FPGA configuration memory. It contains two types of
memory, Static RAM and non-volatile E
device during normal operation and the E
module can be thought of as the hard drive for the ispXPGA configuration and the SRAM as the working configura-
tion memory. There is a one-to-one relationship between SRAM memory and the E
be configured either from the E
Figure 21 shows the different ports and modes that are used in the configuration and programming of the ispXPGA
devices. There are two possible ports that can be used for configuration of the SRAM memory: the ISP port which
supports the IEEE 1149.1 Test Access Port (TAP) Std., accommodates bit-wide configuration. The sysCONFIG
port allows byte-wide configuration of the SRAM configuration memory. When programming the E
only the 1149.1 TAP can be used.
Configuration and programming done through the 1149.1 Test Access Port (TAP) supports both the IEEE Std.
1149.1 Boundary Scan TAP specification and the IEEE Std. 1532 In-System Configuration specification. To config-
ure or program the device using the 1149.1 TAP the device must be in the ISP mode. To configure the SRAM mem-
ory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the device’s SRAM
memory can be configured either from the E
mode. Additionally, the SRAM can be re-configured from the E
TN1026,
modes, timing and wake-up.
Figure 21. ispXP Block Diagram
Supports IEEE 1149.1 Boundary Scan Testability
All ispXPGA devices have boundary scan cells and supports the IEEE 1149.1 standard. This allows functional test-
ing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic
notes. Internal boundary scan registers are linked internally, allowing test data to be shifted in and loaded directly
onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be
linked into a board-level serial scan path for more board level testing.
Security Scheme
A programmable security scheme is provided on the ispXPGA devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, the security scheme prevents read-back of the programmed
ispXP Configuration Usage
Port
Mode
Memory Space
Programming
in seconds
ISP
2
CMOS memory or from an external source, as shown in Figure 21.
Memory Space
ISP 1149.1 TAP Port
BACKGND
E
2
Guidelines, for more in depth information on the different programming
CMOS
2
2
CMOS cells. The static RAM is used to control the functionality of the
CMOS memory cells are used to load the SRAM. The E
2
CMOS memory or from an external source through the sysCONFIG
microseconds
1532
Download in
Power-up
Refresh
19
sysCONFIG Peripheral Port
2
CMOS memory by executing a “REFRESH.” See
Memory Space
sysCONFIG
SRAM
Configuration
in milliseconds
ispXPGA Family Data Sheet
2
CMOS cells. The SRAM can
2
2
CMOS memory,
CMOS memory