SGTL5000XNLA3 Freescale, SGTL5000XNLA3 Datasheet - Page 17

• Manufacturer Part Number: SGTL5000XNLA3
• Manufacturer: Freescale

Specifications of SGTL5000XNLA3

• Single Supply Voltage (typ): 1.8/2.5/3.3V
• Lead Free Status / RoHS Status: Compliant

register. For I2S, Left Justified and Right Justified formats the
left subframe should always be presented first regardless of
the CHIP_I2S_CTRL->LRPOL setting.
master (driven to an external target) or slave (driven from an
external source). When the clocks are in slave mode, they
must be synchronous to SYS_MCLK. For this reason the
Analog Integrated Circuit Device Data
Freescale Semiconductor
The I2S_LRCLK and I2S_SCLK can be programmed as
(SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 0; LRPOL = 0)
(SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 1; LRPOL = 0)
SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 1; LRALIGN = 1; LRPOL = 0)
I2S_DIN, DOUT
I2S_DIN, DOUT
I2S_DIN, DOUT
I2S_LRCLK
I2S_LRCLK
I2S_LRCLK
I2S_SCLK
I2S_SCLK
I2S_SCLK
Right Justified Format (n = bit length)
Left Justified Format (n = bit length)
L
n
L
I2S Format (n = bit length)
(n-1)
L
n
L
(n-1)
CHIP_I2S0_CTRL field values:
CHIP_I2S0_CTRL field values:
CHIP_I2S0_CTRL field values:
Figure 10. I
L
n
L
L01
L
(n-1)
1
L00
L
0
2
S Port Supported Formats
L
0
SGTL5000 can only operate in synchronous mode (see
Clocking) while in I
SYS_MCLK or the output of the PLL when the part is running
in asynchronous mode.
digital interface formats and their associated register
settings.
R
n
In master mode, the clocks will be synchronous to
Figure 10
R
R
(n-1)
n
R
(n-1)
shows functional examples of different common
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
2
S slave mode.
R
n
R
R01
R
(n-1)
1
FUNCTIONAL DEVICE OPERATION
R00
R
0
R0
L
n
L
(n-1)
L
n
SGTL5000
17