SGTL5000XNLA3 Freescale, SGTL5000XNLA3 Datasheet - Page 44

• Manufacturer Part Number: SGTL5000XNLA3
• Manufacturer: Freescale

Specifications of SGTL5000XNLA3

• Single Supply Voltage (typ): 1.8/2.5/3.3V
• Lead Free Status / RoHS Status: Compliant

be changed after reset, and before PLL_POWERUP is set.
Table 32. CHIP_PLL_CTRL 0x0032
44
SGTL500
FUNCTIONAL DEVICE OPERATION
PROGRAMMING EXAMPLES
15:11
BITS
10:0
The
15
Table 32, CHIP_PLL_CTRL 0x0032
14
FRAC_DIVISOR
INT_DIVISOR
INT_DIVISOR
FIELD
13
12
RW
RW
RW
11
RESET
0xA
0x0
10
register may only
This is the integer portion of the PLL divisor. To determine the value of this field, use
the following calculation:
INT_DIVISOR = FLOOR(PLL_OUTPUT_FREQ/INPUT_FREQ)
PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate = 44.1 kHz
else
PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate!= 44.1 kHz
INPUT_FREQ = Frequency of the external MCLK provided if CHIP_CLK_TOP_CTRL-
>INPUT_FREQ_DIV2 = 0x0
else
INPUT_FREQ = (Frequency of the external MCLK provided/2) If
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1
This is the fractional portion of the PLL divisor. To determine the value of this field, use
the following calculation:
FRAC_DIVISOR = ((PLL_OUTPUT_FREQ/INPUT_FREQ) - INT_DIVISOR)*2048
PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate = 44.1 kHz
else
PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate!= 44.1 kHz
INPUT_FREQ = Frequency of the external MCLK provided if CHIP_CLK_TOP_CTRL-
>INPUT_FREQ_DIV2 = 0x0
else
INPUT_FREQ = (Frequency of the external MCLK provided/2) If
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1
9
8
7
6
FRAC_DIVISOR
DEFINITION
5
Analog Integrated Circuit Device Data
4
3
Freescale Semiconductor
2
1
0