ICS9P935AFLF IDT, Integrated Device Technology Inc, ICS9P935AFLF Datasheet

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DDR I/DDR II Phase Lock Loop Zero Delay Buffer Description DDR I/DDR II Zero Delay Clock Buffer Output Features • Low skew, low jitter PLL clock driver • Max frequency supported = 400MHz (DDRII 800) 2 • for ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Pin Description Pin# Pin Name 1 DDRC0 2 DDRT0 3 VDD2.5/1.8 4 DDRT1 5 DDRC1 6 GND 7 VDDA2.5/1.8 8 GND 9 CLK_INT 10 CLK_INC 11 VDD2.5/1.8 12 DDRT2 13 ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Absolute Max Supply Voltage Logic Inputs Ambient Operating Temperature Case Temperature Storage Temperature Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Recommended Operating Condition (see note1 70°C; Supply Voltage AVDD, VDD = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER Supply Voltage Low level input voltage ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Timing Requirements 70°C Supply Voltage AVDD, VDD = 1.8 V +/- 0.1V (unless otherwise stated) A PARAMETER SYMBOL Max clock frequency Application Frequency Range Input clock ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Electrical Characteristics - Input/Supply/Common Output Parameters 70°C; Supply Voltage A A PARAMETER SYMBOL Input High Current I IH Input Low Current I IL Operating Supply I ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Recommended Operating Condition (see note 70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) A PARAMETER SYMBOL Supply Voltage V , ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Timing Requirements =70°C; Supply Voltage A A PARAMETER Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization 3 Switching Characteristics PARAMETER Low-to high ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer 2 General I C serial interface information for the ICS9P935 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D4 • ICS ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Table: Output Control Register Byte 6 Pin # Name - Freq Detect Bit 7 - FB_IN/OUT Bit 6 - DDR_T5/C5 Bit 5 - DDR_T4/C4 Bit 4 - ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer N E1 INDEX INDEX AREA AREA 209 mil SSOP Ordering Information ICS9P935yFLF-T Example: ICS XXXX y F LF- T DDR ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Ordering Information ICS9P935yGLF-T Example: ICS XXXX y G LF- T DDR I/DDR II Phase Lock Loop Zero Delay Buffer TM TM IDT /ICS SYMBOL VARIATIONS Reference Doc.: JEDEC Publication 95, ...

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ICS9P935 DDR I/DDR II Phase Lock Loop Zero Delay Buffer Revision History Rev. Issue Date Description A 2/8/2007 Final Release. B 6/4/2007 Fixed various typos. C 6/14/2007 Added TSSOP Ordering Information. 1. Updated Output Features: Max Frequency Supported. D 6/20/2007 ...