ICS9P935AFLF IDT, Integrated Device Technology Inc, ICS9P935AFLF Datasheet - Page 10

• Manufacturer Part Number: ICS9P935AFLF
• Description: IC BUFFER DDR I/DDR2 PLL 28-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Zero Delay Bufferr

Specifications of ICS9P935AFLF

• Input: Clock
• Output: Clock
• Frequency - Max: 500MHz
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9P935AFLF

IDT
I
I
I
I
I2C Table: All other I2C Registers are Reserved
Byte 10
Byte 15
Table 1: 7-Steps Skew Programming Table
2
2
Byte 8
2
2
C Table: Output Control Register
C Table: Group Skew Control Register
C Table: Revision ID and Vendor ID Register
C Table: Byte Count Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7 Step
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
MSB
TM
11
10
01
00
/ICS
Byte 6
TM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
600 ps
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N/A
N/A
N/A
-
-
-
-
-
-
-
-
11
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
500 ps
N/A
N/A
N/A
10
Revision_ID bit 3
Revision_ID bit 2
Revision_ID bit 1
Revision_ID bit 0
Vendor_ID bit3
Vendor_ID bit2
Vendor_ID bit1
Vendor_ID bit0
400 ps
DDR_T5/C5
DDR_T4/C4
DDR_T3/C3
DDR_T2/C2
DDR_T1/C1
DDR_T0/C0
Freq Detect
FB_IN/OUT
DDR Skw3
DDR Skw2
DDR Skw1
DDR Skw0
DDR Skw3
DDR Skw2
DDR Skw1
DDR Skw0
N/A
N/A
N/A
01
Name
Name
Name
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
300 ps
200 ps
100 ps
0.0 ps
00
Low Frequency Detect
Control Function
Control Function
Control Function
Control Function
Programming b(7:0)
PLL OFF Control
FB_OUT Control
LSB
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
CLKIN to DDR
CLKIN to DDR
Skew Control
Skew Control
Byte Count
Vendor ID
Rev ID
Table 2: 7-Steps Skew Programming Table
7 Step
MSB
11
10
01
00
10
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
-600 ps
N/A
N/A
N/A
11
will be read back, default is
configure how many bytes
See Table 1: 7-Step Skew
See Table 2: 7-Step Skew
Writing to this register will
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Programming Table
Programming Table
OFF
-500 ps
0
0
0
0
-
-
-
-
-
-
-
-
0F = 15 bytes
N/A
N/A
N/A
10
-400 ps
Enable
Enable
Enable
Enable
Enable
Enable
Enable
N/A
N/A
N/A
ON
01
1
1
1
1
-
-
-
-
-
-
-
-
-300 ps
-200 ps
-100 ps
0.0 ps
00
PWD
PWD
PWD
PWD
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
1
0
0
0
0
1
1
1
1
ICS9P935
LSB
REV H 12/1/08