AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 14

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9511
Parameter
DELAY BLOCK ADDITIVE TIME JITTER
1
PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS
Table 7.
Parameter
PHASE NOISE AND SPURIOUS
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
CLK1 = 400 MHz
100 MHz Output
VCXO = 245.76 MHz,
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz
CMOS (OUT4) = 50 MHz (B Output On)
Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000
Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111
Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000
Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111
Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000
Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111
Delay FS = 4 ns (400 μA, 4C) Fine Adj. 00000
Delay FS = 4 ns (400 μA, 4C) Fine Adj. 11111
Delay FS = 5 ns (200 μA, 1C) Fine Adj. 00000
Delay FS = 5 ns (200 μA, 1C) Fine Adj. 11111
Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00000
Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00100
F
245.76 MHz Output
61.44 MHz Output
PFD
Phase Noise @100 kHz Offset
Spurious
Phase Noise @100 kHz Offset
Spurious
= 1.2288 MHz; R = 25, N = 200
1
Min
Typ
<−145
<−97
<−155
<−97
Rev. A | Page 14 of 60
Min
Max
555
Typ
0.61
0.73
0.71
1.2
0.86
1.8
1.2
2.1
1.3
2.7
2.0
2.8
dBc/Hz
dBc
dBc/Hz
dBc
Unit
Max
Depends on VCO/VCXO selection. Measured at LVPECL
clock outputs; ABP = 6 ns; I
VCXO is Toyocom TCO-2112 245.76.
Divide by 1.
Dominated by VCXO phase noise.
First and second harmonics of F
Below measurement floor.
Divide by 4.
Dominated by VCXO phase noise.
First and second harmonics of F
Below measurement floor.
Test Conditions/Comments
Unit
fs rms
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Test Conditions/Comments
Calculated from SNR of ADC method;
F
Interferer(s)
Interferer(s)
Incremental additive jitter
C
= 100 MHz with A
CP
= 5 mA; Ref = 30.72 MHz.
PFD
PFD
.
.
IN
= 170 MHz