AD9511BCPZ Analog Devices Inc, AD9511BCPZ Datasheet - Page 51

• Manufacturer Part Number: AD9511BCPZ
• Description: IC CLOCK DIST 5OUT PLL 48LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution), Divider, PLLr

Specifications of AD9511BCPZ

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Frequency - Max: 1.2GHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.2GHz
• Clock Ic Type: Clock Distribution
• Ic Interface Type: Serial
• Frequency: 1.2GHz
• No. Of Outputs: 5
• No. Of Multipliers / Dividers: 5
• Supply Voltage Range: 3.135V To 3.465V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9511/PCB - BOARD EVAL CLOCK DISTR 48LFCSPAD9511-VCO/PCB - BOARD EVAL CLOCK DISTR 48LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Reg.
Addr.
(Hex)
3D (3E) (3F) <3:2>
3D (3E) (3F) <7:4>
40 (41)
40 (41)
40 (41)
40 (41)
40 (41)
42 (43) (44) <7:0>
45
45
45
45
45
45
45
46 (47)
(48) (49)
Bit(s) Name
<0>
<2:1>
<3>
<4>
<7:5>
<0>
<1>
<2>
<3>
<4>
<5>
<7:6>
<7:0>
Output Level
LVPECL
OUT0
(OUT1)
(OUT2)
Power-Down
LVDS/CMOS
OUT3
(OUT4)
Output Current
Level
LVDS
OUT3
(OUT4)
LVDS/CMOS
Select
OUT3
(OUT4)
Inverted CMOS
Driver
OUT3
(OUT4)
Clock Select
CLK1 Power-Down 1 = CLK1 Input Is Powered Down (Default = 0b).
CLK2 Power-Down 1 = CLK2 Input Is Powered Down (Default = 0b).
Prescaler Clock
Power-Down
REFIN Power-
Down
All Clock Inputs
Power-Down
Description
Output Single-Ended Voltage Levels for LVPECL Outputs.
<3>
0
0
1
1
Not Used
Power-Down Bit for Both Output and LVDS Driver.
0 = LVDS/CMOS on (Default).
1 = LVDS/CMOS Power-Down.
<2>
0
0
1
1
0 = LVDS (Default).
1 = CMOS.
Affects Output Only when in CMOS Mode.
0 = Disable Inverted CMOS Driver (Default).
1 = Enable Inverted CMOS Driver.
Not Used.
Not Used.
0: CLK2 Drives Distribution Section.
1: CLK1 Drives Distribution Section (Default).
1 = Shut Down Clock Signal to PLL Prescaler (Default = 0b).
1 = Power-Down REFIN (Default = 0b).
1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree;
(Default = 0b).
Not Used.
Not Used.
Rev. A | Page 51 of 60
<1>
0
1
0
1
0
1
0
1
<2>
Current (mA)
1.75
3.5 (Default)
5.25
7
Output Voltage (mV)
490
330
805 (Default)
650
Termination (Ω)
100
100
50
50
AD9511