ICS853016AGLF IDT, Integrated Device Technology Inc, ICS853016AGLF Datasheet - Page 8

• Manufacturer Part Number: ICS853016AGLF
• Description: IC FANOUT BUFF LVPECL/ECL 8TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution)r

Specifications of ICS853016AGLF

• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Input: CML, LVDS, LVPECL, SSTL
• Output: ECL, LVPECL
• Frequency - Max: 3GHz
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• Frequency-max: 3GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1160; 800-1160-5; 800-1160; 853016AGLF

T
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
T
This section shows examples of 5V LVPECL output termination.
Figure 3A shows standard termination for 5V LVPECL. The
termination requires matched load of 50
IDT
ERMINATION FOR
ERMINATION FOR
ICS853016
LOW SKEW, 1-TO2, DIFFERENTIAL-TO-3.3V, 5V LVPECL/ECL FANOUT BUFFER
F
RTT =
™
IGURE
/ ICS
5V
™
((V
3A. S
F
3.3V, 5V LVPECL FANOUT BUFFER
FOUT
OH
IGURE
PECL
+ V
TANDARD
OL
2A. LVPECL O
) / (V
Zo = 50 Ohm
Zo = 50 Ohm
1
3.3V LVPECL O
5V LVPECL O
CC
Z
Z
– 2)) – 2
o
o
5V LVPECL O
= 50
= 50
R1
50
Z
o
50
UTPUT
3V
UTPUT
T
UTPUTS
R2
50
UTPUT
ERMINATION
RTT
resistors pull down to
50
V
+
-
T
CC
ERMINATION
5V
FIN
- 2V
PECL
8
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
V
equivalence of Figure 3A. In actual application where the 3V DC
power supply is not available, this approached is normally used.
CC
F
- 2V = 3V at the receiver. Figure 3B shows Thevenin
IGURE
FOUT
5V
F
3B. 5V LVPECL O
IGURE
PECL
2B. LVPECL O
Zo = 50 Ohm
Zo = 50 Ohm
Z
Z
o
o
ICS853016AM REV. B DECEMBER 6, 2007
= 50
= 50
125
84
UTPUT
UTPUT
5V
R3
84
R1
125
3.3V
T
ERMINATION
R4
84
T
125
84
R2
125
ERMINATION
PRELIMINARY
FIN
+
-
E
XAMPLE
PECL