MC100LVEL14DWG ON Semiconductor, MC100LVEL14DWG Datasheet

MC100LVEL14DWG

Manufacturer Part Number

MC100LVEL14DWG

Description

IC CLOCK DISTRIB ECL 1:5 20SOIC

Manufacturer

ON Semiconductor

Series

100LVELr

Type

Fanout Buffer (Distribution), Multiplexerr

Datasheet

1.MC100LVEL14DWR2G.pdf (7 pages)

Specifications of MC100LVEL14DWG

Number Of Circuits

Ratio - Input:output

2:5

Differential - Input:output

Yes/Yes

Input

ECL, PECL

Output

ECL, PECL

Frequency - Max

1GHz

Voltage - Supply

3 V ~ 3.8 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

20-SOIC (7.5mm Width)

Frequency-max

1GHz

Output Logic Level

ECL

Supply Voltage (max)

+/- 3.8 V

Supply Voltage (min)

+/- 3 V

Maximum Operating Temperature

+ 85 C

Minimum Operating Temperature

- 40 C

Mounting Style

SMD/SMT

Multiply / Divide Factor

2:1

Number Of Clock Inputs

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

MC100LVEL14DWGOS

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

MC100LVEL14DWG

Manufacturer:

ON/安森美

Quantity:

20 000

Current page: 1 of 7
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MC100LVEL14

3.3V ECL 1:5 Clock

Distribution Chip

Description

designed explicitly for low skew clock distribution applications. The

device can be driven by either a differential or single-ended ECL or, if

positive power supplies are used, PECL input signal. The LVEL14 is

functionally and pin compatible with the EL14 but is designed to

operate in ECL or PECL mode for a voltage supply range of −3.0 V to

−3.8 V ( or 3.0 V to 3.8 V).

distribution of a lower speed scan or test clock along with the high

speed system clock. When LOW (or left open and pulled LOW by the

input pulldown resistor) the SEL pin will select the differential clock

input.

be enabled/disabled when they are already in the LOW state. This

avoids any chance of generating a runt clock pulse when the device is

enabled/disabled as can happen with an asynchronous control. The

internal flip flop is clocked on the falling edge of the input clock,

therefore all associated specification limits are referenced to the

negative edge of the clock input.

this device only. For single−ended input conditions, the unused

differential input is connected to V

mA. When not used, V

Features

•

November, 2008 − Rev. 9

The MC100LVEL14 is a low skew 1:5 clock distribution chip

The LVEL14 features a multiplexed clock input to allow for the

The common enable (EN) is synchronous so that the outputs will only

The V

For Additional Information, see Application Note AND8003/D

Oxygen Index: 28 to 34

50 ps Output-to-Output Skew

Synchronous Enable/Disable

Multiplexed Clock Input

ESD Protection: Human Body Model >2 kV

The 100 Series Contains Temperature Compensation

PECL Mode Operating Range:

NECL Mode Operating Range:

Internal Input Pulldown Resistors on CLK

Q Output will Default LOW with Inputs Open or at V

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

Moisture Sensitivity Pb = Level 1

Flammability Rating: UL 94 V−0 @ 0.125 in,

Transistor Count = 303 devices

may also rebias AC coupled inputs. When used, decouple V

via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5

= 3.0 V to 3.8 V with V

= 0 V with V

pin, an internally generated voltage supply, is available to

= −3.0 V to −3.8 V

Pb−Free = Level 3

should be left open.

= 0 V

as a switching reference voltage.

and

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

DW SUFFIX

CASE 751D

SOIC−20

ORDERING INFORMATION

http://onsemi.com

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Publication Order Number:

AWLYYWWG

100LVEL14

MARKING

DIAGRAM

MC100LVEL14/D

Related parts for MC100LVEL14DWG

MC100LVEL14DWG Summary of contents

Page 1

MC100LVEL14 3.3V ECL 1:5 Clock Distribution Chip Description The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive ...

Page 2

... Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 2 ...

Page 3

SCLK CLK CLK Warning: All V and V ...

Page 4

Table 4. LVPECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

Page 5

Table 6. AC CHARACTERISTICS V CC Symbol Characteristic f Maximum Toggle Frequency (Figure 2) max t Prop CLK to Q (Diff) PLH t Delay PHL t Part-to-Part Skew SKEW Within-Device Skew (Note 8) t Random Clock Jitter (RMS ...

Page 6

... Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVEL14DW MC100LVEL14DWG MC100LVEL14DWR2 MC100LVEL14DWR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ...

Page 7

... Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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