NB3N551DG ON Semiconductor, NB3N551DG Datasheet

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NB3N551DG

Manufacturer Part Number
NB3N551DG
Description
IC CLK FANOUT BUFFER 1:4 8-SOIC
Manufacturer
ON Semiconductor
Type
Fanout Buffer (Distribution)r
Datasheet

Specifications of NB3N551DG

Number Of Circuits
1
Ratio - Input:output
1:4
Differential - Input:output
No/No
Input
LVCMOS, LVTTL
Output
LVCMOS, LVTTL
Frequency - Max
180MHz
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Frequency-max
180MHz
Number Of Outputs
4
Max Input Freq
180 MHz
Propagation Delay (max)
6 ns @ 3V to 5.5V
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
NB3N551DG
NB3N551DGOS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NB3N551DG
Manufacturer:
ON
Quantity:
1 472
Part Number:
NB3N551DG
Manufacturer:
NSC
Quantity:
235
Part Number:
NB3N551DG
Manufacturer:
ON/安森美
Quantity:
20 000
NB3N551
3.3 V / 5.0 V
Ultra-Low Skew
1:4 Clock Fanout Buffer
Description
for clock distribution in mind. The NB3N551 specifically guarantees
low output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
Features
© Semiconductor Components Industries, LLC, 2009
March, 2009 − Rev. 3
The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed
The output enable (OE) pin three−states the outputs when low.
Input/Output Clock Frequency up to 180 MHz
Low Skew Outputs (50 ps typical)
RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical)
Output goes to Three−State Mode via OE
Operating Range: V
Ideal for Networking Clocks
Packaged in 8−pin SOIC
Industrial Temperature Range
These are Pb−Free Devices
CLK
Figure 1. Block Diagram
DD
= 3.0 V to 5.5 V
OE
Q1
Q2
Q3
Q4
1
†For information on tape and reel specifications,
NB3N551DG
NB3N551DR2G
NB3N551MNR4G
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
8
*For additional marking information, refer to
Device
1
Application Note AND8002/D.
(Note: Microdot may be in either location)
1
ORDERING INFORMATION
3N551 = Specific Device Code
A
L
Y
W
G
I
6K = Specific Device Code
M
G
CLK
Q1
Q2
Q3
PIN CONNECTIONS
http://onsemi.com
= Date Code
= Pb−Free Package
CASE 506AA
1
2
3
4
MN SUFFIX
CASE 751
D SUFFIX
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
SOIC−8
(Pb−Free)
(Pb−Free)
(Pb−Free)
DFN8
Package
SOIC−8
SOIC−8
DFN−8
Publication Order Number:
8
7
6
5
2500/Tape & Reel
1000/Tape & Reel
DIAGRAMS*
8
1
98 Units/Rail
MARKING
OE
V
GND
Q4
Shipping
DD
1
3N551
ALYW
NB3N551/D
G
4

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NB3N551DG Summary of contents

Page 1

... GND ORDERING INFORMATION Device Package Shipping NB3N551DG SOIC−8 98 Units/Rail (Pb−Free) NB3N551DR2G SOIC−8 2500/Tape & Reel (Pb−Free) NB3N551MNR4G DFN−8 1000/Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D ...

Page 2

Table 1. OE, OUTPUT ENABLE FUNCTION Table 2. PIN DESCRIPTION Pin # Name Type 1 I (LV)CMOS/(LV)TTL Input CLK 2 Q1 (LV)CMOS/(LV)TTL Output 3 Q2 (LV)CMOS/(LV)TTL Output 4 Q3 (LV)CMOS/(LV)TTL Output 5 Q4 (LV)CMOS/(LV)TTL Output 6 GND Power 7 V ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply Input/Output Voltage Operating Temperature Range, Industrial A T Storage Temperature Range stg q Thermal Resistance (Junction−to−Ambient) JA Thermal Resistance (Junction−to−Case Thermal Resistance ...

Page 4

Table 5. DC CHARACTERISTICS (V Symbol I Power Supply Current @ 135 MHz, No Load Output HIGH Voltage – Output LOW Voltage – Output HIGH Voltage – ...

Page 5

Figure 2. Phase Noise Plot at 25 MHz at an Operating Voltage of 3.3 V, Room Temperature The above plot captured using Agilent E5052A shows Additive Phase Noise of the NB3N551 device measured with an input source generated by Agilent ...

Page 6

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 7

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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