ADF4113HVBRUZ Analog Devices Inc, ADF4113HVBRUZ Datasheet - Page 14

• Manufacturer Part Number: ADF4113HVBRUZ
• Description: IC CHARGE PUMP HV SYNTH 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4113HVBRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 16mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4113HVEB1Z - BOARD EVALUATION FOR ADF4113HVEVAL-ADF4113EBZ2 - BOARD EVAL FOR ADF4113 1750MHZEVAL-ADF4113EBZ1 - BOARD EVAL FOR ADF4113EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4113HV
DEVICE PROGRAMMING AFTER INITIAL
POWER-UP
After initial power-up of the device, there are two ways to
program the device.
CE Pin Method
1.
2.
3.
4.
After CE goes high, a duration of 1 μs is sometimes required for
the prescaler band gap voltage and oscillator input buffer bias to
reach steady state.
CE can be used to power the device up and down to check for
channel activity. The input register does not need to be repro-
Apply V
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
Program the function latch (10). Program the R counter
latch (00). Program the AB counter latch (01).
Bring CE high to take the device out of power-down. The R
and AB counters resume counting in close alignment.
DD
.
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grammed each time the device is disabled and enabled as long
as it has been programmed at least once after V
applied.
Counter Reset Method
1.
2.
3.
4.
5.
This sequence provides the same close alignment as the initiali-
zation method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but does not trigger synchronous
power-down.
Apply V
Conduct a function latch load (10 in 2 LSBs). As part of
this, load 1 to the F1 bit. This enables the counter reset.
Conduct an R counter load (00 in 2 LSBs).
Conduct an AB counter load (01 in 2 LSBs).
Conduct a function latch load (10 in 2 LSBs). As part of
this, load 0 to the F1 bit. This disables the counter reset.
DD
.
DD
was initially