ADF4113HVBRUZ Analog Devices Inc, ADF4113HVBRUZ Datasheet - Page 6

• Manufacturer Part Number: ADF4113HVBRUZ
• Description: IC CHARGE PUMP HV SYNTH 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of ADF4113HVBRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 16mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4113HVEB1Z - BOARD EVALUATION FOR ADF4113HVEVAL-ADF4113EBZ2 - BOARD EVAL FOR ADF4113 1750MHZEVAL-ADF4113EBZ1 - BOARD EVAL FOR ADF4113EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4113HV
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
TSSOP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LFCSP
Pin No.
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
CPGND
AGND
REF
R
R
AV
R
FIN
FIN
SET
Figure 3. TSSOP Pin Configuration
CP
DD
IN
B
A
1
3
4
5
6
8
2
7
ADF4113HV
(Not to Scale)
Mnemonic
R
CP
CPGND
AGND
RF
RF
AV
REF
DGND
CE
CLK
DATA
LE
MUXOUT
DV
V
TOP VIEW
SET
P
IN
IN
DD
DD
IN
B
A
16
15
14
13
12
11
10
9
Description
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R
I
Charge Pump Output. When enabled, this pin provides ±I
drives the external VCO.
Charge Pump Ground. CPGND is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF.
Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
Analog Power Supply. The power supply can range from 2.7 V to 5.5 V. Decoupling capacitors to the
analog ground plane should be placed as close as possible to this pin. AV
as DV
Reference Input. This pin is a CMOS input with a nominal threshold of V
input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be
ac-coupled.
Digital Ground.
Chip Enable. A Logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device depending on the status of the
Power-Down Bit PD1.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the
scaled reference frequency to be externally accessed.
Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane (1μF, 1nF) should be placed as close as possible to this pin. For best performance, the 1 μF
capacitor should be placed within 2 mm of the pin. The placing of the 1nF capacitor is less critical
but should still be within 5 mm of the pin. DV
Charge Pump Power Supply. V
appropriately.
V
DV
MUXOUT
LE
DATA
CLK
CE
DGND
CP
P
DD
and R
DD
.
SET
is I
CPmax
= 3/R
Rev. A | Page 6 of 20
SET
. Therefore, with R
P
can range from 13.5 V to 16.5 V and should be decoupled
SET
pin is 0.56 V for the ADF4113HV. The relationship between
SET
DD
= 4.7 kΩ, I
must have the same value as AV
CPGND
AGND
AGND
RF
RF
IN
IN
Figure 4. LFCSP Pin Configuration
B
A
1
2
3
4
5
CPmax
CP
ADF4113HV
to the external loop filter; in turn, this
(Not to Scale)
= 640 μA.
TOP VIEW
PIN 1
INDICATOR
DD
DD
/2, and an equivalent
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
must be the same value
DD
.