SI5316-C-GM Silicon Laboratories Inc, SI5316-C-GM Datasheet - Page 2

• Manufacturer Part Number: SI5316-C-GM
• Description: IC PREC JITTER ATTENUATOR 36-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Jitter Attenuatorr

Specifications of SI5316-C-GM

• Number Of Circuits: 1
• Package / Case: 36-QFN
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 710MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 710MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 19.38 MHz
• Output Frequency Range: 19.38 MHz to 710 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5316
Table 1. Performance Specifications
(V
2
Temperature Range
Supply Voltage
Supply Current
Input/Output Clock Fre-
quency (CKIN1, CKIN2,
CKOUT)
3-Level Input Pins
Input Mid Current
Input Clocks (CKIN1, CKIN2)
Differential Voltage Swing
Common Mode Voltage
Rise/Fall Time
Duty Cycle
(Minimum Pulse Width)
Output Clock (CKOUT)
Common Mode
Differential Output Swing
Single Ended Output Swing
Rise/Fall Time
Duty Cycle Uncertainty
PLL Performance
Jitter Generation
LVPECL output,
f
BW[1:0] = HM
Notes:
IN
DD
= f
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
OUT
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Manual. In most designs, an external resistor voltage divider is recommended.
Parameter
= 622.08
CKN
CKN
CKN
CKO
Symbol
CKO
CKN
V
J
V
CK
I
V
V
I
IMM
OCM
GEN
T
DD
OD
DD
SE
A
VCM
DPP
TRF
TRF
F
DC
DC
A
= –40 to 85 ºC)
1
measured at 50% point
LVPECL format output
Whichever is smaller
CMOS format output
FRQSEL[1:0] = MM
FRQSEL[1:0] = MH
f
FRQSEL[1:0] = LM
FRQSEL[1:0] = ML
FRQSEL[1:0] = LH
FRQSEL[1:0] = LL
OUT
f
Differential 100 Ω
OUT
50 kHz–80 MHz
12 kHz–20 MHz
Test Condition
Disable Mode
See Note 2.
2.5 V ±10%
3.3 V ±10%
100 Ω load
line-to-line;
1.8 V ±5%
line-to-line
= 622.08 MHz
20–80%
LVPECL
20–80%
LVPECL
= 19.44 MHz
Rev. 0.4
V
DD
19.38
38.75
155.0
310.0
620.0
2.97
2.25
1.71
77.5
0.25
Min
–40
–40
0.9
1.0
1.1
1.1
0.5
–2
40
—
—
—
—
—
—
—
– 1.42
2
0.32
0.31
Typ
165
217
194
230
3.3
2.5
1.8
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
DD
178.25
22.28
44.56
89.13
356.5
710.0
Max
3.63
2.75
1.89
1.95
0.93
0.42
0.41
243
220
215
350
1.9
1.4
1.7
1.9
85
11
60
40
—
– 1.25
2
ps rms
ps rms
MHz
Unit
V
V
mA
mA
mA
µA
ºC
ns
ns
ps
ps
%
V
V
V
V
V
V
V
V
PP
PP