SI5316-C-GM Silicon Laboratories Inc, SI5316-C-GM Datasheet - Page 3

• Manufacturer Part Number: SI5316-C-GM
• Description: IC PREC JITTER ATTENUATOR 36-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Jitter Attenuatorr

Specifications of SI5316-C-GM

• Number Of Circuits: 1
• Package / Case: 36-QFN
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 710MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 710MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 19.38 MHz
• Output Frequency Range: 19.38 MHz to 710 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1. Performance Specifications
(V
Table 2. Absolute Maximum Ratings
Jitter Transfer
External Reference Jitter
Transfer
Phase Noise
f
Subharmonic Noise
f
Spurious Noise
f
Package
Thermal Resistance
Junction to Ambient
Notes:
DC Supply Voltage
LVCMOS Input Voltage
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ); All pins except
CKIN+/CKIN–
ESD MM Tolerance; All pins except CKIN+/CKIN–
ESD HBM Tolerance (100 pF, 1.5 kΩ); CKIN+/CKIN–
ESD MM Tolerance; CKIN+/CKIN–
Latch-Up Tolerance
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
IN
IN
IN
DD
= f
= f
= f
1. For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
2. This is the amount of leakage that the 3-level input can tolerate from an external driver. See the Family Reference
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
OUT
OUT
OUT
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Manual. In most designs, an external resistor voltage divider is recommended.
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Parameter
= 622.08
= 622.08
= 622.08
Parameter
J
Symbol
SP
SP
CKO
PKEXTN
J
θ
SUBH
SPUR
PK
JA
PN
A
= –40 to 85 ºC)
(n > 1, n x F3 < 100 MHz)
1
Phase Noise @ 100 kHz
(Continued)
Max spur @ n x F3
Test Condition
100 kHz offset
100 Hz offset
10 kHz offset
1 MHz offset
1 kHz offset
Still Air
Offset
Rev. 0.4
Symbol
T
V
T
V
STG
JCT
DIG
DD
Min
—
—
—
—
—
—
—
—
—
—
–0.3 to (V
–0.5 to 3.6
–55 to 150
–55 to 150
Value
JESD78 Compliant
–130
–110
–117
700
0.05
200
150
Typ
–65
–95
–90
–98
30
38
2
DD
+ 0.3)
–100
–125
–110
Max
–85
–75
–50
–87
0.1
—
—
Si5316
Unit
kV
ºC
ºC
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
V
V
V
V
V
ºC/W
Unit
kHz
dBc
dBc
dB
3