SI5326A-C-GM Silicon Laboratories Inc, SI5326A-C-GM Datasheet - Page 34

• Manufacturer Part Number: SI5326A-C-GM
• Description: IC ANY-RATE MULTI/ATTEN 36-QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5326A-C-GM

• Package / Case: 36-QFN
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.4GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 1.4GHz
• Max Input Freq: 710 MHz
• Max Output Freq: 945 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Outputs: 2
• Supply Current: 251 mA
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Si5326
Reset value = 1111 1111
34
Register 21.
Name
Type
6:2
Bit
Bit
7
1
0
INCDEC_PIN
CK1_ACTV_
CKSEL_PIN
INCDEC_
Reserved
R/W
PIN
Name
D7
PIN
Force 1
INCDEC_PIN.
Determines how coarse skew adjustments can be made. The adjustments can be made
via hardware using the INC/DEC pins or via software using the CLAT register.
0: INC and DEC inputs ignored; use CLAT register to adjust skew.
1: INC and DEC inputs control output phase increment/decrement.
Reserved.
CK1_ACTV_PIN.
The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the
CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin con-
trolled clock selection is being used. (See CKSEL_PIN)
0: CS_CA output pin tristated.
1: Clock Active status reflected to output pin.
CKSEL_PIN.
If manual clock selection is being used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when
AUTOSEL_REG = Manual.
0: CS_CA pin is ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CS_CA input pin controls clock selection.
D6
D5
R
Reserved
Rev. 1.0
D4
R
Function
D3
R
D2
R
CK1_ACTV
_PIN
R/W
D1
CKSEL_
R/W
PIN
D0