ISL12028IV27Z-T Intersil, ISL12028IV27Z-T Datasheet - Page 20

• Manufacturer Part Number: ISL12028IV27Z-T
• Description: IC RTC EEPROM LP 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12028IV27Z-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12028IV27Z-TTR

Afterwards, the address counter would point to location 6 on
the page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over-written by the new data, one byte at a
time (refer to Figure 22).The master terminates the Data
Byte loading by issuing a stop condition, which causes the
ISL12028 to begin the non-volatile write cycle. As with the
byte write operation, all inputs are disabled until completion
of the internal write cycle. Refer to Figure 21 for the address,
acknowledge, and data transfer sequence.
STOPS AND WRITE MODES
Stop conditions that terminate write operations must be sent
by the master after sending at least 1 full data byte and it’s
associated ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
ISL12028 resets itself without performing the write. The
contents of the array are not affected.
.
ACKNOWLEDGE POLLING
Disabling of the inputs during non-volatile write cycles can
be used to take advantage of the typical 5mS write cycle
SIGNALS FROM
SIGNALS FROM
THE MASTER
SDA BUS
THE SLAVE
ADDRESS POINTER ENDS
6 BYTES
FIGURE 22. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
SIGNALS FROM
SIGNALS FROM
ADDRESS = 5
AT ADDR = 5
THE MASTER
THE SLAVE
A
R
S
T
T
SDA BUS
20
1
ADDRESS
SLAVE
1
1
1
A
R
S
T
T
0
1
A
C
K
FIGURE 20. BYTE WRITE SEQUENCE
FIGURE 21. PAGE WRITE SEQUENCE
ADDRESS
0 0 0 0 0 0 0
ISL12028, ISL12028A
SLAVE
ADDRESS 1
1
1
1
WORD
0
A
C
K
0 0 0 0 0 0 0
ADDRESS 1
A
C
K
WORD
ADDRESS 0
time. Once the stop condition is issued to indicate the end of
the master’s byte load operation, the ISL12028 initiates the
internal non-volatile write cycle. Acknowledge polling can
begin immediately. To do this, the master issues a start
condition followed by the Memory Array Slave Address Byte
for a write or read operation (AEh or AFh). If the ISL12028 is
still busy with the non-volatile write cycle then no ACK will be
returned. When the ISL12028 has completed the write
operation, an ACK is returned and the host can proceed with
the read or write operation. Refer to the flow chart in
Figure 24. Note: Do not use the CCR Slave byte (DEh or
DFh) for Acknowledge Polling.
Read Operations
There are three basic read operations: Current Address
Read, Random Read, and Sequential Read.
Current Address Read
Internally the ISL12028 contains an address counter that
maintains the address of the last word read incremented by
one. Therefore, if the last read was to address n, the next read
operation would access data from address n + 1. On power-up,
ADDRESS
WORD
A
C
K
10
ADDRESS 0
WORD
A
C
K
1 ≤ n ≤ 16 fOR EEPROM ARRAY
1 ≤ n ≤ 8 FOR CCR
A
C
K
DATA
6 BYTES
(1)
DATA
ADDRESS
A
C
K
15
S
O
P
T
DATA
(n)
November 30, 2010
A
C
K
S
O
P
T
FN8233.9