ISL12028IV27Z-T Intersil, ISL12028IV27Z-T Datasheet - Page 21

• Manufacturer Part Number: ISL12028IV27Z-T
• Description: IC RTC EEPROM LP 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12028IV27Z-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12028IV27Z-TTR

the sixteen bit address is initialized to 0h. In this way, a current
address read immediately after the power on reset can
download the entire contents of memory starting at the first
location. Upon receipt of the Slave Address Byte with the R/W
bit set to one, the ISL12028 issues an acknowledge, then
transmits eight data bits. The master terminates the read
operation by not responding with an acknowledge during the
ninth clock and issuing a stop condition. Refer to Figure 23 for
the address, acknowledge, and data transfer sequence.
SIGNALS FROM
SIGNALS FROM
THE MASTER
SDA BUS
FIGURE 23. CURRENT ADDRESS READ SEQUENCE
THE SLAVE
FIGURE 24. ACKNOWLEDGE POLLING SEQUENCE
ISSUE MEMORY ARRAY SLAVE
AFH (READ) OR AEH (WRITE)
CYCLE COMPLETE. CONTINUE
ENTER ACK POLLING
NORMAL READ OR
WRITE COMMAND
COMMAND SEQUENCE?
RETURNED?
COMPLETED BY
NON-VOLATILE WRITE
ISSUE START
ISSUING STOP.
SEQUENCE
CONTINUE
A
R
S
T
T
PROCEED
BYTE LOAD
ADDRESS BYTE
1
YES
YES
ACK
ADDRESS
21
SLAVE
1
1
1
NO
NO
1
A
C
K
ISSUE STOP
DATA
ISSUE STOP
ISL12028, ISL12028A
O
S
P
T
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
RANDOM READ
Random read operations allow the master to access any
location in the ISL12028. Prior to issuing the Slave Address
Byte with the R/W bit set to zero, the master must first
perform a “dummy” write operation.
The master issues the start condition and the slave address
byte, receives an acknowledge, then issues the word
address bytes. After acknowledging receipt of each word
address byte, the master immediately issues another start
condition and the slave address byte with the R/W bit set to
one. This is followed by an acknowledge from the device and
then by the 8-bit data word. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition. Refer to Figure 25 for the address,
acknowledge, and data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 25. The ISL12028 then goes
into standby mode after the stop and all bus activity will be
ignored until a start is detected. This operation loads the new
address into the address counter. The next Current Address
Read operation will read from the newly loaded address.
This operation could be useful if the master knows the next
address it needs to read, but is not ready for the data.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address
read or random address read. The first data byte is
transmitted as with the other modes; however, the master
now responds with an acknowledge, indicating it requires
additional data. The device continues to output data for each
acknowledge received. The master terminates the read
operation by not responding with an acknowledge and then
issuing a stop condition.
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
counter for read operations increments through all page and
column addresses, allowing the entire memory contents to
be serially read during one operation. At the end of the
address space, the counter “rolls over” to the start of the
address space and the ISL12028 continues to output data
for each acknowledge received. Refer to Figure 26 for the
acknowledge and data transfer sequence.
November 30, 2010
FN8233.9