M48T58Y-70MH1F STMicroelectronics, M48T58Y-70MH1F Datasheet - Page 11

• Manufacturer Part Number: M48T58Y-70MH1F
• Description: IC TIMEKPR SRAM 64KBIT 5V 28SOIC
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T58Y-70MH1F

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC, 28-SOH (8.48mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4722-2

M48T58, M48T58Y
4
Figure 6.
A0-A12
E1
E2
W
DQ0-DQ7
WRITE mode
The M48T58/Y is in the WRITE mode whenever W and E1 are low and E2 is high. The start
of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge
of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2.
The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low
for a minimum of t
initiation of another READ or WRITE cycle. Data-in must be valid t
WRITE and remain valid for t
avoid bus contention; although, if the output bus has been activated by a low on E1 and G
and a high on E2, a low on W will disable the outputs t
WRITE enable controlled, WRITE AC waveform
E1HAX
tAVE1L
tAVE2H
tAVWL
or t
tWLQZ
E2LAX
WHDX
Doc ID 2412 Rev 7
tAVWH
from chip enable or t
tWLWH
afterward. G should be kept high during WRITE cycles to
VALID
tAVAV
tDVWH
DATA INPUT
tWHDX
WHAX
WLQZ
from WRITE enable prior to the
after W falls.
tWHQX
DVWH
tWHAX
prior to the end of
WRITE mode
AI00963
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