PCF2123BS/1,512 NXP Semiconductors, PCF2123BS/1,512 Datasheet - Page 22

• Manufacturer Part Number: PCF2123BS/1,512
• Description: IC CLOCK HVQFN16
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF2123BS/1,512

• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Clock, Calendar, Alarm, Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.1 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: SPI
• Supply Current: 250 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5051-5; 935286382512

NXP Semiconductors
PCF2123
Product data sheet
Table 26.
The minute and second flag (bit MSF) is set logic 1 when either the seconds or the
minutes counter increments according to the currently enabled interrupt. The flag can be
read and cleared by the interface. The status of bit MSF does not affect the INT pulse
generation. If the MSF flag is not cleared prior to the next coming interrupt period, an INT
pulse will still be generated.
The purpose of the flag is to allow the controlling system to interrogate the PCF2123 and
identify the source of the interrupt, i.e., minute or second, countdown timer or alarm.
Table 27.
The duration of both of these timers will be affected by the register Offset_register (see
Section
consistent.
Minute interrupt (bit MI)
Minute interrupt (bit MI)
0
1
0
1
0
1
0
1
Fig 14. INT example for MI and SI
MSF when only MI enabled
INT when only MI enabled
8.9). Only when the Offset_register has the value 00h the periods will be
MSF when SI enabled
INT when SI enabled
In this example, TI_TP is set to logic 1 resulting in
not cleared after an interrupt.
Effect of bits MI and SI on INT generation
Effect of MI and SI on MSF
seconds counter
minutes counter
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 22 December 2010
Second interrupt (bit SI)
0
0
1
1
Second interrupt (bit SI)
0
0
1
1
58
59
59
11



Result
no interrupt generated
an interrupt once per minute
an interrupt once per second
an interrupt once per second
Result
MSF never set
MSF set when minutes counter
increments
MSF set when seconds counter
increments
MSF set when seconds counter
increments
Hz wide interrupt pulse and the MSF flag is
00
12
SPI Real time clock/calendar
00
PCF2123
© NXP B.V. 2010. All rights reserved.
01
001aaf905
22 of 61