ISL12008IB8Z-T Intersil, ISL12008IB8Z-T Datasheet - Page 11

• Manufacturer Part Number: ISL12008IB8Z-T
• Description: IC RTC I2C LO-POWER 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12008IB8Z-T

• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year, the year 2100 is not. The
ISL12008 does not correct for the leap year in the year 2100.
Control and Status Registers
Addresses [07h to 0Bh]
The Control and Status Registers consist of the Status
Register, Interrupt and Alarm Register, Analog Trimming and
Digital Trimming Registers.
Status Register (SR) [Address 0Bh]
The Status Register is located in the memory map at
address 0Bh. This is a volatile register that provides either
control or status of RTC failure, battery mode, alarm trigger,
crystal oscillator status, ReSeal™ and auto reset of status
bits.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12008 internally) when
the device powers up after having lost all power to the device
(both V
whether V
the supplies does not set the RTCF bit to “1”. On power-up
after a total power failure, all registers are set to their default
states and the clock will not increment until at least one byte
is written to the clock register. The first valid write to the RTC
section after a complete power failure resets the RTCF bit to
“0” (writing one byte is sufficient).
BATTERY BIT (BAT)
This bit is set to a “1” when the device enters battery backup
mode. This bit can be reset either manually by the user or
automatically reset by enabling the auto-reset bit (see ARST
bit). A write to this bit in the SR can only set it to “0”, not “1”.
ALARM BIT (ALM)
These bits announce if the alarm matches the real time
clock. If there is a match, the respective bit is set to “1”. This
bit can be manually reset to “0” by the user or automatically
reset by enabling the auto-reset bit (see ARST bit). A write to
this bit in the SR can only set it to “0”, not “1”.
NOTE: An alarm bit that is set by an alarm occurring during an SR
read operation will remain set after the read operation is complete.
Default
ADDR
0Bh
DD
ARST
7
0
DD
and V
TABLE 2. STATUS REGISTER (SR)
or V
BAT
6
0
0
BAT
go to 0V). The bit is set regardless of
is applied first. The loss of only one of
RESEAL
5
0
11
4
0
0
3
0
0
ALM BAT RTCF
2
0
1
1
0
1
ISL12008
ReSeal (RESEAL)
The ReSeal™ enables the device enter into the InterSeal™
Battery Saver mode after manufacture testing for board
functionality. The factory default setting of this bit is “0”. The
RESEAL must be set to “0” to enable the battery function
during normal operation or full functional testing. To use the
ReSeal function, simply set RESEAL bit to “1” after the
testing is completed. It will enable the InterSeal™ Battery
Saver mode and prevents battery current drain before it is
first used.
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT,
ALM and TMR status bits only. When ARST bit is set to “1”,
these status bits are reset to “0” after a valid read of the
respective status register (with a valid STOP condition).
When the ARST is cleared to “0”, the user must manually
reset the BAT and ALM bits.
Interrupt Control Register (INT) [Address 08h]
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
V
V
power mode and the V
V
about 600nA when using LPMODE = “1” with V
(See “Typical Performance Curves” on page 6: I
with LPMODE ON and OFF.)
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
bit is cleared to “0”, the alarm function is disabled. ALME bit is
set to “0” at power-up.
Oscillator Fail Register (OF) [Address 09h]
OSCILLATOR FAIL BIT (OF)
This bit is set to a “1” when the X1 pin has no oscillation.
This bit can be reset when the X1 has crystal oscillation and
a write to “0”. This bit can only be written as “0” and not as a
“1”. The OF bit is set to “1” at power up from a complete
power down (V
08h
Default
09h
Default
ADDR
ADDR
BAT
DD
DD
< V
< V
TABLE 4. INTERRUPT CONTROL REGISTER (INT)
supply will be used when V
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
TRIP
BAT
7
0
0
OF
7
1
. With LPMODE = “1”, the device will be in low
ALME LPMODE
- V
DD
6
0
BATHYS
6
0
0
and V
BAT
5
0
5
0
0
. There is a supply current saving of
BAT
supply will be used when
are removed). Address 1, bit 7
4
0
0
DD
4
0
0
3
0
0
< V
BAT
3
0
0
2
0
0
- V
September 26, 2008
2
0
0
DD
BATHYS
DD
1
0
0
= 5V.
vs V
1
0
0
FN6690.1
0
0
0
CC
and
0
0
0