ISL12008IB8Z-T Intersil, ISL12008IB8Z-T Datasheet - Page 9

• Manufacturer Part Number: ISL12008IB8Z-T
• Description: IC RTC I2C LO-POWER 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12008IB8Z-T

• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

Also provided is the ability to adjust the crystal capacitance
when the ISL12008 switches from V
mode. See “Battery Backup Mode (V
(V
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101000x” and reads or writes to addresses
[00h:1Fh]. The defined addresses and default values are
described in Table 1. Address 12h to 1Eh are not used.
Reads or writes to 12h to 1Eh will not affect operation of the
device but should be avoided.
REGISTER ACCESS
The contents of address 00h to 07h can be modified by
performing a byte or a page write operation directly to any
register address. In a page write operation to address 00h to
07h, the address will wrap around from 07h to 00h. All the
other registers (Address 08h to 11h and 1Fh) can be
modified by performing a byte write operation.
The registers are divided into 3 sections. These are:
There are no addresses above 1Fh.
Address 12h to 1Eh are not used. Reads or writes to 12h to
1Eh will not affect operation of the device but should be
avoided.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and Alarm registers, the read
operation latches all clock registers into a buffer, so an
update of the clock does not change the time being read. A
sequential read will not result in the output of data from the
memory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus. After a
read, the address remains at the previous address +1 so the
user can execute a current address read and continue
reading the next register. In a sequential read, the address
will warp around at address 07h to 00h; therefore, please
use byte read operation to read the registers after
address 07h.
1. Real Time Clock (8 bytes): Address 00h to 06h, and 1Fh.
2. Control and Status (4 bytes): Address 07h to 0Bh.
3. Alarm (6 bytes): Address 0Ch to 11h.
DD
Address 1Fh is Sub-Second register and it is a read-only.
)” on page 7.
9
DD
BAT
to battery backup
) to Normal Mode
ISL12008
September 26, 2008
FN6690.1