ISL12029IV27AZ Intersil, ISL12029IV27AZ Datasheet - Page 17

• Manufacturer Part Number: ISL12029IV27AZ
• Description: IC RTC/CALENDAR EEPROM 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12029IV27AZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPTION 2 - LEGACY POWER CONTROL MODE
(DEFAULT FOR ISL12029)
The Legacy Mode follows conditions set in X1226 products.
In this mode, switching from V
comparing the voltages and the device operates from
whichever is the higher voltage. Care should be taken when
changing from Normal to Legacy Mode. If the V
higher than V
unless the battery is disconnected or the voltage decreases,
the device will no longer operate from V
situation on initial power-up, then I
be possible. For these applications, the ISL12029A should be
used.
To select the Option 2, BSW bit in the Power Register must
be set to “BSW = 1.”
• Normal Mode (V
To transition from the V
conditions must be met:
V
• Battery Backup Mode (V
The device will switch from the V
following condition occurs:
V
The Legacy Mode power control conditions are illustrated in
Figure 15.
Power-on Reset
Application of power to the ISL12029 activates a Power-on
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
- It prevents the system microprocessor from starting to
- It prevents the processor from operating prior to
- It allows time for an FPGA to download its configuration
- It prevents communication to the EEPROM, greatly
When V
typically 250ms the circuit releases RESET, allowing the
DD
DD
operate with insufficient voltage.
stabilization of the oscillator.
prior to initialization of the circuit.
reducing the likelihood of data corruption on power-up.
V
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
BAT
< V
> V
DD
BAT
BAT
exceeds the device V
+V
- V
DD
BATHYS
BATHYS
, then the device will enter battery backup and
OFF
DD
) to Battery Backup Mode (V
DD
V
DD
to V
BAT
17
DD
) to Normal Mode (V
BAT
BAT
to V
RESET
2
C communication may not
mode, the following
BAT
VOLTAGE
to V
DD
threshold value for
is simply done by
DD
. If that is the
mode when the
BAT
ON
ISL12029, ISL12029A
BAT
voltage is
DD
)
)
IN
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
NOTE: If the V
minimum of 1.8V and the V
to V
I
power will need to be cycled to 0V together to allow normal
operation again.
Watchdog Timer Operation
The Watchdog timer time-out period is selectable. By writing
a value to WD1 and WD0, the Watchdog timer can be set to
3 different time-out periods or off. When the Watchdog timer
is set to off, the Watchdog circuit is configured for low power
operation (see Table 8).
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the Watchdog timer counter, resetting the
period of the counter back to the maximum. If another
START fails to be detected prior to the Watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh Watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode (see Figure 3).
In battery mode, the Watchdog timer function is disabled.
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
compares the level of the V
voltage (V
below V
V
V
Power-up and power-down waveforms are shown in
Figure 4. The LVR circuit is to be designed so the RESET
signal is valid down to V
When the LVR signal is active, unless the part has been
switched into the battery mode
in-progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
2
C communications will not operate. The V
DD
RESET
DD
WD1
line rises above V
1
1
0
0
voltage, then the RESET output may stay low and the
, then the RESET output will remain asserted low.
RESET
TABLE 8. WATCHDOG TIMER OPERATION
RESET
. The reset pulse will time-out 250ms after the
BAT
), then generates a RESET pulse if it is
WD0
voltage drops below the data sheet
1
0
1
0
RESET
DD
DD
DD
= 1.0V.
. If the V
power cycles to 0V then back
line versus a preset threshold
,
the completion of an
DD
DURATION
disabled
250ms
750ms
remains below
1.75s
BAT
December 16, 2010
and V
FN6206.10
DD