MAXQ3181-RAN+ Maxim Integrated Products, MAXQ3181-RAN+ Datasheet - Page 32

• Manufacturer Part Number: MAXQ3181-RAN+
• Description: IC AFE POLYPHASE LO-PWR 28-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAXQ3181-RAN+

• Number Of Channels: 8
• Power (watts): 35mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Bits: -

Low-Power, Active Energy, Polyphase AFE
32
Bit:
Name:
Reset:
Bit:
Name:
Reset:
13, 7:3
BIT
15
14
12
11
10
______________________________________________________________________________________
9
8
2
1
0
EDSPRDY When set, this flag causes the IRQ pin to become active.
ECHSCH
EDSPOR
EDCHA
EPWRF
ENOZX
EEOVF
NAME
EOC
EUV
EOV
EDSPOR
—
15
—
0
7
0
When set, the DSPOR flag causes the IRQ pin to become active.
Reserved.
When set, this flag causes the IRQ pin to become active when the direction of real energy flow has
been observed to have changed (that is, from toward the load to away from the load, or from away from
the load to toward the load).
When set, this flag causes the IRQ pin to become active when the MAXQ3181 has failed to detect zero
crossings on one or more voltage channels for at least one DSP cycle.
When set, this flag causes the IRQ pin to become active when the absolute instantaneous voltage
level in one or more voltage channels failed to exceed the trip level set in the UVLVL (Undervoltage
Level) register for one DSP cycle.
When set, this flag causes the IRQ pin to become active when the absolute instantaneous voltage
level in one or more voltage channels has exceeded the trip level set in the OVLVL (Overvoltage Level)
register.
When set, this flag causes the IRQ pin to become active when absolute instantaneous current in one
or more current channels has exceeded the trip level set in the OCLVL (Overcurrent Level) register.
When set, this flag causes the IRQ pin to become active when one or more energy accumulators have
an overflow condition from their MSB.
When set, this flag enables the IRQ pin to become active when a CHKSUM change is detected.
When set, this flag causes the IRQ pin to become active when a power-supply failure is imminent and
the supervisory processor should begin taking steps to save its state and prepare for a loss of power.
EDSPRDY
14
—
0
6
0
13
—
—
0
5
0
EDCHA
12
—
0
4
0
Interrupt Mask Register (IRQ_MASK) (0x006)
FUNCTION
ENOZX
11
—
0
3
0
EEOVF
EUV
10
0
2
0
ECHSCH
EOV
9
0
1
0
EPWRF
EOC
8
0
0
0