AD9246BCPZ-125 Analog Devices Inc, AD9246BCPZ-125 Datasheet - Page 19

• Manufacturer Part Number: AD9246BCPZ-125
• Description: IC ADC 14BIT 125MSPS 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9246BCPZ-125

• Data Interface: Serial, SPI™
• Design Resources: Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051)
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Number Of Converters: 3
• Power Dissipation (max): 425mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 125MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9246-125EBZ - BOARD EVAL FOR 125MSPS AD9246AD9246-105EBZ - BOARD EVAL FOR 105MSPS AD9246
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CLOCK
CLOCK
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in Figure 47. The
AD9513/AD9514/AD9515
lent jitter performance.
CLOCK
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 48. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock
drivers offers excellent jitter performance.
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
directly drive CLK+ from a CMOS gate, while bypassing the
CLK− pin to ground using a 0.1 μF capacitor in parallel with a
39 kΩ resistor (see Figure 49). CLK+ may be directly driven
from a CMOS gate. This input is designed to withstand input
voltages up to 3.6 V, making the selection of the drive logic
voltage very flexible. When driving CLK+ with a 1.8 V CMOS
signal, biasing the CLK− pin with a 0.1 μF capacitor in parallel
with a 39 kΩ resistor (see Figure 49) is required. The 39 kΩ
resistor is not required when driving CLK+ with a 3.3 V CMOS
signal (see Figure 50).
CLOCK
INPUT
INPUT
INPUT
CLOCK
INPUT
INPUT
50Ω
1
50Ω
1
50Ω RESISTORS ARE OPTIONAL
50Ω RESISTORS ARE OPTIONAL
1
1
Figure 46. Transformer Coupled Differential Clock
50Ω
0.1µF
Figure 48. Differential LVDS Sample Clock
Figure 47. Differential PECL Sample Clock
0.1µF
0.1µF
50Ω
0.1µF
0.1µF
50Ω
100Ω
1
1
ADT1–1WT, 1:1Z
LVDS DRIVER
CLK
CLK
CLK
PECL DRIVER
CLK
MIN-CIRCUITS
AD951x
AD951x
XFMR
0.1µF
family of clock drivers offers excel-
240Ω
0.1µF
0.1µF
AD9510/AD9511/AD9512/
SCHOTTKY
HSMS2812
DIODES:
240Ω
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9246
CLK+
CLK–
AD9246
AD9246
ADC
ADC
ADC
Rev. A | Page 19 of 44
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9246 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling, or falling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9246. Noise and distortion performance are nearly flat
for a wide range of duty cycles when the DCS is on, as shown in
Figure 31.
Jitter in the rising edge of the input is still of paramount
concern and is not reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that needs to be considered in applications
where the clock rate can change dynamically. This requires a
wait time of 1.5 μs to 5 μs after a dynamic clock frequency
increase (or decrease) before the DCS loop is relocked to the
input signal. During the time period the loop is not locked, the
DCS loop is bypassed, and the internal device timing is
dependent on the duty cycle of the input clock signal. In such
an application, it may be appropriate to disable the duty cycle
stabilizer. In all other applications, enabling the DCS circuit is
recommended to maximize ac performance.
CLOCK
CLOCK
INPUT
INPUT
1
50Ω RESISTOR IS OPTIONAL
50Ω
50Ω
1
50Ω RESISTOR IS OPTIONAL
Figure 49. Single-Ended 1.8 V CMOS Sample Clock
Figure 50. Single-Ended 3.3 V CMOS Sample Clock
0.1µF
0.1µF
1
1
VCC
VCC
1kΩ
1kΩ
1kΩ
1kΩ
CMOS DRIVER
CMOS DRIVER
AD951x
AD951x
0.1µF
OPTIONAL
OPTIONAL
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
CLK+
CLK–
AD9246
CLK+
CLK–
AD9246
AD9246
ADC
ADC