HI5812JIPZ Intersil, HI5812JIPZ Datasheet - Page 10

• Manufacturer Part Number: HI5812JIPZ
• Description: IC ADC 12BIT 50KSPS LP HS 24DIP
• Manufacturer: Intersil

Specifications of HI5812JIPZ

• Number Of Bits: 12
• Sampling Rate (per Second): 50k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 25mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Theory of Operation
HI5812 is a CMOS 12-Bit Analog-to-Digital Converter that
uses capacitor-charge balancing to successively approximate
the analog input. A binarily weighted capacitor network forms
the A/D heart of the device. See the block diagram for the
HI5812.
The capacitor network has a common node which is
connected to a comparator. The second terminal of each
capacitor is individually switchable to the input, V
V
During the first three clock periods of a conversion cycle, the
switchable end of every capacitor is connected to the input
and the comparator is being auto-balanced at the capacitor
common node.
During the fourth period, all capacitors are disconnected
from the input; the one representing the MSB (D11) is
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NO.
REF
-.
DRDY
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
V
D10
D11
OEM
V
V
V
V
V
STRT
CLK
OEL
V
NAME
SS
AA
AA
IN
REF
REF
DD
-
+
+
-
TABLE 1. PIN DESCRIPTIONS
Output flag signifying new data is available.
Goes high at end of clock period 15. Goes low
when new conversion is started.
Bit 0 (Least Significant Bit, LSB).
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
Bit 8.
Bit 9.
Digital Ground (0V).
Bit 10.
Bit 11 (Most Significant Bit, MSB).
Three-State Enable for D4-D11. Active low input.
Analog Ground, (0V).
Analog Positive Supply. (+5V) (See text.)
Analog Input.
Reference Voltage Positive Input, sets 4095
code end of input range.
Reference Voltage Negative Input, sets 0 code
end of input range.
Start Conversion Input Active Low, recognized
after end of clock period 15.
CLK Input or Output. Conversion functions are
synchronized to positive going edge. (See
text.)
Three-State Enable for D0 D3. Active Low Input.
Digital Positive Supply (+5V).
10
DESCRIPTION
REF
+ or
HI5812
connected to the V
capacitors to V
charges balance out, will indicate whether the input was
above
period, the comparator output is stored and the MSB
capacitor is either left connected to V
was high) or returned to V
comparison to be at either
At the end of periods 5 through 14, capacitors representing
D10 through D1 are tested, the result stored, and each
capacitor either left at V
At the end of the 15th period, when the LSB (D0) capacitor is
tested, (D0) and all the previous results are shifted to the
output registers and drivers. The capacitors are reconnected
to the input, the comparator returns to the balance state, and
the data-ready output goes active. The conversion cycle is
now complete.
Analog Input
The analog input pin is a predominately capacitive load that
changes between the track and hold periods of the
conversion cycle. During hold, clock period 4 through 15, the
input loading is leakage and stray capacitance, typically less
than 5µA and 20pF.
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have
low enough impedance to dissipate the current spike by the
end of the tracking period as shown in Figure 18. The
amount of charge is dependent on supply and input
voltages. The average current is also proportional to clock
frequency.
As long as these current spikes settle completely by end of
the signal acquisition period, converter accuracy will be
preserved. The analog input is tracked for 3 clock cycles.
With an external clock of 750kHz the track period is 4µs.
DRDY
CLK
I
IN
CONDITIONS: V
1
FIGURE 18. TYPICAL ANALOG INPUT CURRENT
/
20mA
10mA
2
0mA
of (V
5V
0V
5V
0V
REF
REF
REF
+ - V
-. The capacitor-common node, after the
V
IN
DD
+ terminal; and the remaining
REF
REF
= 4.608V, CLK = 750kHz, T
= V
REF
3
+ or at V
/
AA
-). At the end of the fourth
4
-. This allows the next
or
+ = 5.0V, V
200ns/DIV.
1
/
4
REF
of (V
REF
REF
+ (if the comparator
-.
REF
+ = 4.608V,
+ - V
A
REF
= 25
o
-).
C